Abstract: Methods and apparatus are provided for reducing the amount of resources allocated for handling multiplexing in a processor. Characteristics associated with processing blocks are analyzed. Operand restrictions and register groups can be configured to allow the use of more resource efficient multiplexing circuitry in a processor.

Abstract: A processor for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the programs.

Abstract: A processor for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the programs.

Abstract: The execution status of pipeline processing is highly visualized by appropriately displaying processes forming loops in a simplified manner. A loop-information storage unit stores loop-defining information specifying the address of an instruction that causes a pipeline process forming a loop. An operation-information storage unit stores operation information that includes the address of an instruction input into a pipeline and information indicating the execution status of a pipeline process caused by the instruction. A loop determination unit determines whether each pipeline process indicated by the operation information forms a loop by referring to the loop-defining information. An output unit outputs visualization information indicating, in a visually comprehensible manner, the execution status of a pipeline process that has been determined to form a loop for a predetermined number of executions of the loop and the execution status of a pipeline process that has been determined to form no loop.

Abstract: A first performance indicator associated with a first agent is received from a workforce management system. A second performance indicator associated with a second agent is also received from the workforce management system. The first agent and the second agent are ranked in a queue of available agents based upon at least the first performance indicator and the second performance indicator. This produces a first queue rank associated with the first agent. An incoming call directed to the queue of available agents is received. An agent to service the incoming call is selected from the queue of available agents based upon the first queue rank.

Abstract: A functional-level instruction-set computing (FLIC) architecture executes higher-level functional instructions such as lookups and bit-compares of variable-length operands. Each FLIC processing-engine slice has specialized processing units including a lookup unit that searches for a matching entry in a lookup cache. Variable-length operands are stored in execution buffers. The operand length and location in the execution buffer are stored in fixed-length general-purpose registers (GPRs) that also store fixed-length operands. A copy/move unit moves data between input and output buffers and one or more FLIC processing-engine slices. Multiple contexts can each have a set of GPRs and execution buffers. An expansion buffer in a FLIC slice can be allocated to a context to expand that context's execution buffer for storing longer operands.

Abstract: A computer implemented method, a processor chip, a computer program product, and a data processing system managing a link stack. The data processing system utilizes speculative pushes onto and pops from the link stack. The link stack comprises a set of entries, and each entry comprises a set of state bits. A speculative push of a first instruction is received onto the data stack, and the first instruction is stored into a first entry of the set of entries. A first bit is set to indicate that the first instruction is a valid instruction. A second bit is set to indicate that the first instruction has been speculatively pushed onto the link stack. The link stack pointer control is updated to indicate that the first entry is a top-of-data stack entry.

Abstract: A system and method provides branch target buffer (BTB) allocation. When a branch instruction is received, a branch target address that corresponds to the branch instruction is determined. A determination is made whether the branch target address is presently stored in a branch target buffer (BTB). When the branch target address is not presently stored in the branch target buffer, an entry in the branch target buffer is identified to receive the branch target address. A value in a field within the identified entry in the branch target buffer, such as a postponement flag (PF), is used to selectively override a replacement decision defined by predetermined branch target buffer allocation criteria. In one form, if a branch is taken, the identified entry is replaced with the branch target address in response to determining that the value in the field within the identified entry has a predetermined value.

Abstract: A predication technique for out-of-order instruction processing provides efficient out-of-order execution with low hardware overhead. A special op-code demarks unified regions of program code that contain predicated instructions that depend on the resolution of a condition. Field(s) or operand(s) associated with the special op-code indicate the number of instructions that follow the op-code and also contain an indication of the association of each instruction with its corresponding conditional path. Each conditional register write in a region has a corresponding register write for each conditional path, with additional register writes inserted by the compiler if symmetry is not already present, forming a coupled set of register writes. Therefore, a unified instruction stream can be decoded and dispatched with the register writes all associated with the same re-name resource, and the conditional register write is resolved by executing the particular instruction specified by the resolved condition.

Abstract: A system, method and program product for retaining a logic state of a processor pipeline architecture are disclosed. A comparator is positioned between two stages of the processor pipeline architecture. A storage capacitor is coupled between a storage node of the comparator and a ground to store an output of the early one of the two stages. A reference logic is provided, which has the same value as the output of the early stage. A logic storing and dividing device is coupled between the reference logic and a reference node of the comparator to generate a logic at the reference node, which is a fraction of the reference logic, and to retain a logic state of the information stored on the storage capacitor. Further mechanisms are provided to determine validity of data stored in the logic storing and dividing device.

Abstract: In at least one embodiment, a processor includes at least one execution unit that executes instructions and instruction sequencing logic, coupled to the at least one execution unit, that fetches instructions from a memory system for execution by the at least one execution unit. The instruction sequencing logic including branch target address prediction circuitry that stores a branch target address prediction associating a first instruction fetch address with a branch target address to be used as a second instruction fetch address. The branch target address prediction circuitry includes delay logic that, in response to at least a tag portion of a third instruction fetch address matching the first instruction fetch address, delays access to the memory system utilizing the second instruction fetch address if no branch target address prediction was made in an immediately previous cycle of operation.

Abstract: A single register file may be addressed using both scalar and SIMD instructions. That is, subsets of registers within a multi-addressable register file according to the illustrative embodiments, are addressable with different instruction forms, e.g., scalar instructions, SIMD instructions, etc., while the entire set of registers may be addressed with yet another form of instructions, referred to herein as Vector-Scalar Extension (VSX) instructions. The operation set that may be performed on the entire set of registers using the VSX instruction form is substantially similar to that of the operation sets of the subsets of registers. Such an arrangement allows legacy instructions to access subsets of registers within the multi-addressable register file while new instructions, i.e. the VSX instructions, may access the entire range of registers within the multi-addressable register file.

Abstract: A branch target buffer (BTB) receives, from a processor, a current fetch group address which corresponds to a current fetch group including a plurality of instructions. In response to the current fetch group address resulting in a group hit in the BTB, the BTB provides to the processor a branch target address corresponding to a branch instruction within the current fetch group which is indicated by a control field as valid and predicted taken. The BTB generates the branch target address using an unshared lower order target portion, corresponding to the branch instruction and located within the entry of the BTB which caused the group hit, and one of a shared higher order target portion located within the entry of the BTB which caused the group hit or a higher order portion of the current fetch group address based on a value of the control field.

Abstract: A reconfigurable processor (RP) structure is provided, and particularly, a multi-mode providing apparatus including an exclusive coarse-grained array unit for each mode and a multi-mode providing method thereof are provided.

Abstract: In at least one embodiment, a processor includes an execution unit and instruction sequencing logic that fetches instructions from a memory system for execution by the execution unit. The instruction sequencing logic includes branch logic that outputs predicted branch target addresses for use as instruction fetch addresses. The branch logic includes a branch target address prediction circuitry concurrently holding a first entry providing storage for a first branch target address prediction associating a first instruction fetch address with a first branch target address to be used as an instruction fetch address and a second entry providing storage for a second branch target address prediction associating the first instruction fetch address with a different second branch target address. The first entry indicates a first instruction address type for the first instruction fetch address, and the second entry indicates a second instruction address type for the first instruction fetch address.

Abstract: A mechanism enabling a processor in a multiprocessor complex to function as a coprocessor to execute a specific function. The method includes a mechanism for activating a coprocessor to function as a coprocessor as well as a mechanism to execute a coprocessor request on the system. The present invention also provides a mechanism for efficient processor to processor communication for processors coupled to a common bus. Overall system performance is enhanced by significantly reducing the use of hardware interrupts for processor to processor communication.

Abstract: A method for selectively accelerating early instruction processing including receiving an instruction data that is normally processed in an execution stage of a processor pipeline, wherein a configuration of the instruction data allows a processing of the instruction data to be accelerated from the execution stage to an address generation stage that occurs earlier in the processor pipeline than the execution stage, determining whether the instruction data can be dispatched to the address generation stage to be processed without being delayed due to an unavailability of a processing resource needed for the processing of the instruction data in the address generation stage, dispatching the instruction data to be processed in the address generation stage if it can be dispatched without being delayed due to the unavailability of the processing resource, and dispatching the instruction data to be processed in the execution stage if it can not be dispatched without being delayed due to the unavailability of the pro

Abstract: A computer processor that includes a plurality of execution pipelines, each execution pipeline including a configuration of one or more execution units of the processor, each execution pipeline characterized by an execution pipeline type, each execution pipeline type determined according to the types of computer program instructions executed in each execution pipeline; a plurality of hardware threads of execution, each hardware thread including computer program instructions characterized by instruction types, each hardware thread including sequences of instructions of a same instruction type, the sequences interspersed with instructions of other types; and an instruction dispatcher capable of dispatching instructions preferentially during a predefined preference period from a preferred hardware thread to a particular execution pipeline in dependence upon whether the preferred hardware thread presents a sequence of instructions, ready for execution from the preferred hardware thread, of a type for execution in

Abstract: Hardware and software techniques for interrupt detection and response in a scalable pipelined array processor environment are described. Utilizing these techniques, a sequential program execution model with interrupts can be maintained in a highly parallel scalable pipelined array processing containing multiple processing elements and distributed memories and register files. When an interrupt occurs, interface signals are provided to all PEs to support independent interrupt operations in each PE dependent upon the local PE instruction sequence prior to the interrupt. Processing/element exception interrupts are supported and low latency interrupt processing is also provided for embedded systems where real time signal processing is required. Further, a hierarchical interrupt structure is used allowing a generalized debug approach using debut interrupts and a dynamic debut monitor mechanism.

Abstract: Illustrative embodiments determine the data type of the operand being accessed as well as analyze the data value subrange of the input operand data type. If the operand's data type does not match the required format of the instruction being processed, a determination is made as to whether a subrange of data values of the data type of the input operand is supported natively. If the subrange of data values of the input operand is not supported natively, then a format conversion is performed on the data and the instruction may then operate on the data. Otherwise, the data may be operated on directly by the instruction without a format conversion operation and thus, the conversion is not performed.