Abstract: An apparatus comprising a first power combiner/divider network and a second power combiner/divider network. The first power combiner/divider network splits a first electromagnetic signal into split signals that are connectable to signal processor(s). The second power combiner/divider network combines processed signals into a second electromagnetic signal. The apparatus includes a three-dimensional coaxial microstructure.

Abstract: A foreign-object detecting device includes a first coil, a second coil arranged adjacent to the first coil and having the same winding direction as that of the first coil, and foreign-object detecting circuitry. The foreign-object detecting circuitry outputs a first detection signal to an outside or inside terminal of the first coil, outputs a second detection signal having an inverted phase to an outside or inside terminal of the second coil, causes one of the first and second detection signal to flow clockwise, causes the other detection signal to flow counterclockwise to generate a combined magnetic field across a center of the first and a center of the second coil, measures an amount of change in an impedance value of the first or second coils, and determines that a foreign object is present within the combined magnetic field, based on the amount of change.

Abstract: An interpolative divider includes a look ahead sigma delta modulator circuit to generate divide values according to a divide ratio. A plurality of M storage elements are coupled to the sigma delta modulator to store the divide values, M being at least 2. A selector circuit selects the respective divide values and supplies the divide values to a portion of an interpolative divider circuit, the portion including a divider and a phase interpolator. The interpolative divider generates an output clock signal having a first clock period that may be determined by the first and second divide values. The M storage elements are loaded by a clock signal that is slower than the output clock signal by at least half.

Abstract: A standard voltage circuit includes an operational amplifier, first and second diodes, a resistance element, and a dummy leak generation circuit. The first diode is electrically connected to a first node of a first line which is disposed on an output terminal side of the operation amplifier and is electrically connected to a first input terminal of the operation amplifier through the first node. The second diode is electrically inserted connected to a second node of a second line which is disposed on the output terminal side of the operation amplifier and is electrically connected to a second input terminal of the operation amplifier through the second node. The resistance element is electrically connected to the second node in series with the second diode. The dummy leak generation circuit is electrically connected to one of the first line and the second line.

Abstract: A battery is provided including a battery cell having main top and bottom surfaces, and a plurality of side surfaces; and at least one resin section including a cured resin that covers at least three of the plurality of side surfaces of the battery cell, but that does not cover substantially all of the top and bottom surfaces of the battery cell.

Abstract: In a system for performing clock generation for each semiconductor device, synchronization between the semiconductor devices is achieved without causing a count value in a counter to be discontinuously changed.

Abstract: An apparatus for driving a thyristor in an alternating-current power grid includes a non-isolated power supply circuit and a throttling circuit. One terminal of a power supply input of the non-isolated power supply circuit is connected to a first terminal of the thyristor. The other terminal of the power supply input is connected to another phase of the power supply relative to the first terminal or a neutral lead. The non-isolated power supply circuit forms a signal trigger loop through the throttling circuit, a second terminal of the thyristor and the first terminal of the thyristor. A control terminal of the throttling circuit is connected to a third terminal of the thyristor. The apparatus of the present invention has advantages of occupying a small space and having a simple circuit, a great instantaneous triggering current, a high cost effectiveness, and a low power consumption.

Abstract: A pulse width filtering circuit for filtering pulse signals includes an input transition detection circuit detecting change of state of an input signal, including a first transition from a low signal to a high signal and a second transition from the high signal to the low signal; a first delay circuit determining whether the high signal from the first transition is maintained longer than a first period and, if so, generating a first output indicative of the first transition, after the first period; a second delay circuit determining whether the low signal from the second transition is maintained for longer than a second period and, if so, generating a second output indicative of the second transition, after the second period; and a switching circuit connected to the first and second delay circuits and selectively outputting the first output and the second output, based on the state of the input signal.

Abstract: A power semiconductor drive circuit includes a parallel circuit connected to a gate of a power semiconductor element and constituted by two transistors for setting gate resistance of the power semiconductor element; a gate voltage monitoring circuit connected to the gate of the power semiconductor element and the parallel circuit, wherein a monitoring voltage is set in the gate voltage monitoring circuit to monitor a gate voltage of the power semiconductor element; a signal delay circuit to delay an output signal of the gate voltage monitoring circuit; and a gate control circuit to change the magnitude of combined resistance of the parallel circuit based on an output signal output from the signal delay circuit.

Abstract: A superposition principle of waveform based on conceptions of waveform continuity and flexible regulation of voltage proposes three concepts, respectively being flexible AC transformation, flexible power transmission and transformation and flexible voltage regulation; proposes three new technologies, respectively being a transient impedance technology, a flexible stepless voltage regulation technology and a flexible stepped voltage regulation technology; proposes three new products, being an AC voltage regulating electronic switch, a transient impedance transformer and a high-speed voltage regulating transformer; proposes six high-voltage power grid connection methods, being a power grid connection method type of a transient impedance transformer, a power grid connection method of a transient impedance step up auto transformer and the like; and proposes a new reactive compensation connection method for a reactive compensation device.

Abstract: Methods, and apparatus for determining inertia within a synchronous area of an electric power grid are described. A frequency characteristic relating to a frequency of electricity flowing in the electric power grid is measured, a magnitude relating to a power flow modulation is determined based on data relating to power characteristics of one or more power units arranged to consume electric power from and/or provide real and/or reactive electric power to the electric power grid, and a frequency response characteristic associated with at least one area of the electric power grid is determined on the basis of the measured frequency characteristic and the determined magnitude characteristic. This enables frequency response characteristics within a synchronous area of the electric power grid to be easily determined.

Abstract: Various embodiments of the present technology may comprise methods and apparatus for an integrated circuit (IC). The methods and apparatus may comprise an integrated circuit comprising a sensor circuit and a driver circuit coupled to the sensor circuit. The driver circuit may include an amplifier configured to generate a bias voltage, a signal converter circuit coupled to the amplifier, and a control circuit coupled to the amplifier. The control circuit may comprise a switch responsive to a control signal and a transistor coupled to the switch.

Abstract: Sharing of load current in desired ratios between multiple electrical voltage sources is achieved without coupling between the sources by controlling a selection switch to select each voltage source for a proportion of the time at a high rate, the switching rate components being prevented from being seen by either the load or the sources through use of low-pass filters.

Abstract: Provided is an IO interface level shift circuit, comprising: an intermediate level generation circuit (11) and a level shift circuit (12). The intermediate level generation circuit is configured to provide an intermediate level Vdd_io of an IO interface. The level shift circuit is configured to convert an external logical signal into a signal in an internal power domain of a chip according to the intermediate level Vdd_io of the IO interface. Also provided are an IO interface level shift method and a storage medium. The interface level shift circuit enables level shift on an external IO signal at any level in a voltage withstanding domain of a device without adding a power domain suitable for an external IO level in the circuit.

Abstract: The present invention relates to a power management system (PMS) for multiple energy storage systems (ESS) that is for integrated management of the system having multiple ESS for controlling a frequency and having a hierarchical control structure. The PMS for ESS comprises: a plurality of ESS; a local management system (LMS) for managing one or more ESS of the plurality of ESS for each local unit; an ESS Controller (ESSC) for general management of the LMS, judging a state of the LMS and determining an output value of one or more ESS in the LMS, and transmitting the determined output value to the respective ESS; and a PMS for general management of the entire system comprising the plurality of ESS, the LMS and the ESSC, judging the state of the entire system and participating in a power grid frequency control market through a grid operator contract, controlling the output of the LMS, and adjusting a control parameter for output control.

Abstract: This application relates to methods and apparatus for phase locked loops. A phase-and-frequency detector (101) receives a reference clock signal (CKref) and a feedback signal (SFB) and outputs a first adjustment signal (U) that is modulated between respective first and second signal levels to provide control pulses indicating that an increase in frequency required for phase and frequency lock, and a second adjustment signal (D) that is modulated between respective first and second signal levels to provide control pulses indicating that a decrease in frequency required for phase and frequency lock. First and second time-to-digital converters (201-1 and 201-2) receive the first and second adjustment signals respectively and output respective first and second digital signals indicative of the duration of said control pulses.

Abstract: A POR circuit for a secondary supply domain of an IC. A bias and reference circuit provides startup current and a reference voltage for a comparator. The comparator compares the reference voltage with a primary supply voltage and develops a bias current. The bias and reference circuit and the comparator includes a VGS loop which mirrors the bias current to develop the reference voltage. When the comparator switches, the bias current is at the low quiescent current level. A level shift and isolation circuit initially isolates a primary POR signal from the secondary domain. When the comparator switches, the primary POR signal is detected and level shifted to control the reset state. The delay circuit senses ramping of the secondary supply voltage and provides a delayed secondary POR signal a predetermined time period after the secondary supply voltage achieves a predetermined voltage threshold to additionally control the reset state.

Abstract: An inverted funnel-shaped columnar tower (115) includes a window region (120), a heat absorbing surface (130), an air entrance (116) and exit (117). Solar energy passes through the window region and heats the heat absorbing surface. A plurality of fans (145), each connected to a generator (150), are suspended within the tower and extract energy from convectively rising air, generating electricity. A fan (160) outside the tower intercepts wind and turns an internal fan (145?) that aids the convective flow, providing a self-starting feature. A plurality of rotors (100) with wings (705) are connected in groups to generators (725) and all are arranged adjacent the tower. The rotors intercept wind energy and deliver it to the generators for conversion to electricity. The rotors include a flap (800) that predetermines the direction of rotation of the rotor, providing a second self-starting feature. The convection and wind-capture functions operate independently.

Abstract: The present technology relates to a notch filter capable of easily obtaining a desired frequency characteristic. In an N-path filter unit, any one of a plurality of N capacitors is selected as a signal path through which a signal passes, so that the capacitor serving as the signal path is temporally switched. A plurality of N-path filter units is cascade-connected and a capacitor is inserted to a connection point between the N-path filter units. The present technology may be applied to the notch filter which eliminates a blocker and the like, for example.

Abstract: The invention disclosed a signal processing system and method thereof, applicable to an environment providing accurate output frequency. By using the signal processing system, the stable output voltage (AMP OUT) of the error amplifier is inputted to the input of the voltage controlled oscillator (VCO), the output frequency (Fvco) of the VCO is provided to the input of fractional-N frequency divider for digital division. The output of the fractional-N frequency divider (Fo) is provided to the input of the frequency to voltage converter for frequency/voltage conversion. Then, the low pass filter is used to filter out the ripple of the output voltage (V1) of the frequency to voltage converter and the trebling jitter of the output of the fractional-N frequency divider. The signal processing system of the present invention utilizes the voltage locked loop property and digital frequency division to achieve accurate frequency output.