Abstract: A method and device for input offset cancellation utilizing a latched comparator that is configurable as a linear amplifier capable of sampling and cancelling offset in the inputs to the latched comparator. The latched comparator is configured according to three control signals for operation in three operating intervals. During a first operating interval, the latched comparator is configured as a linear amplifier that samples the offset at the inputs to the latched comparator. Based on the sampled offset, the linear amplifier cancels the offset in the inputs to the latched comparator. During a second operating interval, the latched comparator reverts to operation as comparator and the inputs to the latch are reset. During a third interval, the latch resolves the inputs to the comparator and generates an output signal indicating.

Abstract: A power on reset circuit including an inverter powered by a first power domain, the inverter including a data input coupled to a power rail of a second power domain; logic circuitry coupled with an output of the inverter, the logic circuitry having a control signal output; and wherein, during a power up operation, the first power domain powers up before the second power domain powers up. Upon power up of the first power domain, the inverter can output a high signal to the logic circuitry and output a low signal to the logic circuitry in response to power up of the second power domain. The logic circuitry is further configured to output a first value for a control signal in response to the first power domain powering up and configured to output a second value for the control signal in response to the second power domain powering up.

Abstract: In a clock generating circuit having a plurality of injection-locking oscillators, a first one of the injection-locking oscillators is enabled to output a free-running reference clock signal and a control value is generated based at least in part on a frequency relationship between the free-running reference clock signal and an input timing signal. In accordance with the control value, a selected one of the injection-locking oscillators is enabled to generate an output clock signal that is frequency-locked with respect to the input timing signal.

Abstract: A gate driver circuit for a half bridge or full bridge output driver stage having a high side branch connected to one or more high side transistors and a low side branch connected to one or more low side transistors. A high side gate driver and a low side gate driver receive input signals at a low voltage level and output signals at a high voltage level as gate driving signals for the high side transistors and low side transistors. Each of the high side and the low side branches of the gate driver includes a set-reset latch having a signal output that is fed as a gate signal to the corresponding transistor of the half bridge or full bridge driver. A differential capacitive level shifter circuit receives the input signals at a low voltage level and outputs high voltage signals to drive the set and reset inputs of the set-reset latch.

Abstract: Described is a latch which comprises: a first AND-OR-invert (AOI) logic gate; and a second AOI logic gate coupled to the first AOI logic gate, wherein the first and second AOI logic gates have respective first and second keeper devices coupled to a power supply node. Described is a flip-flop which comprises: a first latch including: a first AOI logic gate; and a second AOI logic gate coupled to the first AOI logic gate, wherein the first and second AOI logic gates have respective first and second keeper devices coupled to a power supply, the first latch having an output node; and a second latch having an input node coupled to the output node of the first latch, the second latch having an output node to provide an output of the flip-flop.

Abstract: Apparatus and methods are disclosed that utilize magnetically differential loop filter capacitor elements that are physically positioned adjacent voltage-controlled oscillator (VCO) inductor/s in the device layout of a phase locked loop (PLL) circuit. Such a PLL circuit may be employed, for example, to produce a PLL output signal for RF receivers, RF transmitters, RF transceivers and any other type of circuit configured to utilize a PLL output signal having a phase that is based on the phase of an input signal.

Abstract: An integrated circuit (IC), a method of testing the IC, and a method of manufacturing the IC are provided. The IC includes analog circuitry, digital circuitry, at least one first connector, and a switching unit operatively coupled with the at least one first connector and configured to, if a first signal is received, couple the analog circuitry and the at least one first connector, and, if a second signal is received, couple the digital circuitry and the at least one first connector.

Abstract: A packaged inverse diode device exhibits superior commutation robustness. The device includes a stack of inverse diodes disposed within a housing. Each adjacent pair of inverse diodes is bonded together by an intervening DMB (Direct Metal Bonded) substrate structure. At one end of the stack of diode dice and DMB substrate structures is attached a first metal terminal. A second metal terminal is attached to the other end of the stack. The two terminals serve as package terminals of the overall device. In a novel method, the device undergoes severe commutation. A large forward current is made to flow through the diode stack, followed by a rapid reversal of the voltage across the stack to a large reverse polarity voltage. Despite a substantial rate of change of the commutation current at the onset of the reverse voltage condition, the inverse diode device is not damaged.

Abstract: An apparatus includes first and second input transistors receiving respective first and second input signals, and a feedback circuit coupled to the first and second input transistors. The first and second input transistors provide first and second nodes with first and second currents according to values of the first and second input signals, respectively, when the feedback circuit is turned on. The first and second input transistors produce a reset value on the nodes when the feedback circuit is turned off. A method includes resetting, using first and second input transistors, respectively, values of first and second nodes to a reset value, providing first and second currents to the nodes using the first and second input transistors according to values of first and second input signals, and determining the values of the nodes according to the values of the first and second input signals.

Abstract: Disclosed herein is an low power output stage coupled between a supply node and a ground node, configured to drive an output, and controlled by first, second, and third control nodes. A current sinking circuit controlled by an input signal and configured to sink current from the first and second control nodes when the input signal transitions to a first logic level, thereby resulting in decoupling of the output stage from the ground node and sourcing of current to the output by the output stage. When the input signal transitions to a second logic level different than the first logic level, the current sinking circuit sinks current from a third control node, thereby resulting in decoupling of the output stage from the supply node and sinking of current from the output by the output stage.

Abstract: A driver for a power field-effect transistor includes a first and second circuits that apply respective charge currents to a gate of the power field-effect transistor when a control signal has a first logic value and the voltage between the gate and the source is smaller than a first threshold voltage and greater than a second threshold voltage. Third and fourth circuits apply respective discharge currents to the gate when the control signal has a second logic value and the voltage between the gate and the source is greater than a third threshold voltage and smaller than a fourth threshold voltage. The driver may include at least one field-effect transistor configured to generate at least one of the first, second, third or fourth threshold voltage.

Abstract: A vehicle includes: an electrical storage device; an inlet; a power conversion unit; and an ECU configured to: (a) determine whether the connector connected to the inlet is a charge connector for charging the electrical storage device or a discharge connector for feeding electric power to an external device on the basis of a first signal that is supplied via the inlet; (b) determine whether the discharge connector is a power extracting connector for feeding electric power to a single load or a facility connector for feeding electric power to a facility on the basis of a second signal that is supplied via the inlet when the ECU determines that the connector is the discharge connector; and (c) control an exchange of electric power between the inlet and the electrical storage device with the use of the power conversion unit on the basis of the determination of the connector.

Abstract: A receiver device in a coupled coil system for wireless energy transfer includes a receiver coil and a load device operatively connected to the receiver coil and configured to receive a signal from the receiver coil. As one example, the load device is a rechargeable battery. An adjusting filter is included in the receiver device and is operatively connected between the receiver coil and the load device. The adjusting filter can be used to transform the effective resistance or impedance of the load as presented to the transformer during energy transfer so that the effective resistant or impedance of the load is maintained at a substantially constant level, and the signal received by the load device is maintained at a substantially constant level.

Abstract: A brown-out detector and power-on-reset circuit can be used to monitor a supply voltage to determine when brown-out and power-on events occur and provide the appropriate reset signal in response. The circuit can include a comparator to generate the reset signal and a first monitoring circuit that operates in conjunction with a second monitoring circuit to provide an input voltage to the comparator. The first monitoring circuit can incorporate a bandgap circuit and can be used to control the input voltage based on the comparison of the supply voltage and a corresponding supply voltage threshold. The second monitoring circuit can incorporate a diode and can be used when the supply voltage is lower than a threshold voltage for the bandgap circuit. The second monitoring circuit can be used to control the input voltage based on a comparison of the supply voltage and a threshold voltage for the diode.

Abstract: A current sensing system and method for wireless energy transfer may include a printed circuit board, wherein the printed circuit board may include at least a first layer, a second layer, and a third layer. A loop of conductive material may be included, wherein the loop of conductive material may include a diameter D3 on the second layer. A coil of conductive material may be included, wherein the coil of conductive material may have at least 2 turns, wherein a majority of the coil of conductive material may occupy the first layer and the third layer with an outer diameter D1 and an inner diameter D2, connected through each of the first, second, and third layers. The loop of conductive material may be coupled to the coil of conductive material.

Abstract: Apparatuses and methods are provided that minimize the effects of dark-current pulses. For example, in one embodiment of the invention, a method is provided where a first pixel is struck (i.e., a primary pixel). Pixels struck within a fixed time frame after the primary pixel is struck are referred to as secondary pixels. After a short fixed time frame has expired, the number of primary and secondary pixels is added. If the count exceeds a threshold, the primary pixel was activated by the first (or early) photon from a true gamma event. If the threshold is not met then it is likely the primary pixel generated a dark pulse that should be ignored.

Abstract: According to one embodiment, a signal monitoring circuit includes a first comparator circuit that compares an input signal with a first reference value to output a first output signal, a second comparator circuit that compares the input signal with a second reference value different from the first reference value to output a second output signal, a delay time detecting circuit that detects a time difference between times at which the first and second output signals are output, and a threshold-value comparator circuit that compares the detected time difference with a predetermined threshold value to output the comparison result.

Abstract: A semiconductor circuit includes a first circuit and a second circuit. The first circuit determines a logic level of a second node and a logic level of a third node, on the basis of a logic level of input data, a logic level of a clock signal, and a logic level of a first node. The second circuit determines the logic level of the first node, on the basis of the logic level of the clock signal, the logic level of the second node and the logic level of the third node. The first circuit comprises a sub-circuit and a first transistor. The first circuit determines the logic level of the second node, on the basis of the logic level of the input data and the logic level of the first node. The first transistor is gated to the logic level of the clock signal to connect the third node with the second node.

Abstract: A semiconductor device comprises a two-dimensional (2D) material layer, the 2D material layer comprising a channel region in between a source region and a drain region; a first gate stack and a second gate stack in contact with the 2D material layer, the first and second gate stack being spaced apart over a distance; the first gate stack located on the channel region of the 2D material layer and in between the source region and the second gate stack, the first gate stack arranged to control the injection of carriers from the source region to the channel region and the second gate stack located on the channel region of the 2D material layer; the second gate stack arranged to control the conduction of the channel region.

Abstract: A frequency includes an input terminal, an output terminal, a transistor having a gate terminal which receives input of a signal including a first frequency from the input terminal, a source terminal and a drain terminal connected to the output terminal by a main line, an output matching circuit provided in the main line, the output matching circuit shutting off the first frequency while allowing an output frequency multiplied from the first frequency to pass therethrough, a branch line including a power supply terminal for connection to a power supply, the branch line branching off from a branch point in the main line, and a first diode provided in the branch line, the first diode having an anode connected to the power supply terminal and a cathode connected on the branch point side.