Abstract: Circuitry for controlling a non-overlap time for a first switch and a second switch is described. Within a first state, the first switch is closed and the second switch is open, and within a second state, the first switch is open and the second switch is closed. The control circuitry has a first auxiliary switch and a second auxiliary switch. The control circuitry determines whether during a transition from the first state to the second state a current has flown through the serial arrangement of the first and second auxiliary switches. The control means adapts a non-overlap time between the first and second control signals for controlling a following transition from the first state to the second state, dependent on whether during said transition between the first and second states a current has flown through the serial arrangement of the first and second auxiliary switches.

Abstract: An eye pattern measurement apparatus includes: an eye pattern monitoring device, performing first sampling on a data signal by sequentially using scan clock signals having different phases to obtain a plurality of scan data signals; and a data aligning device, connected to the eye pattern monitoring device, receiving the scan data signals outputted by the eye pattern monitoring device, performing phase-shift on the first clock signal to generate a synchronization clock signal, synchronizing the scan data signals with the synchronization clock signal, and outputting the synchronized scan data signals.

Abstract: Apparatus and techniques described herein can include a load circuit comprising a direct current (DC) input terminal, and a source circuit comprising a direct current (DC) output terminal coupled to the DC input terminal of the load circuit. The source circuit can include a source control circuit configured to provide a current-limited DC output voltage and monitor the current-limited DC output voltage to detect an authentication signal provided at the DC output terminal by the load circuit, the load circuit configured to modulate the voltage at the DC output terminal using a pull-down circuit. The load circuit can be configured to compare the supply voltage at the DC input terminal to a reference voltage and, in response, energize other portions of the load circuit when the input current provided the DC input terminal is sufficient as indicated at least in part by the comparison.

Abstract: A phase-inverted clock generation circuit is provided, where sources of a first PMOS and a second PMOS are connected to a power source, drains of the first PMOS and the second PMOS are connected to a source of a third PMOS, and a drain of the third PMOS is connected to a drain of a third NMOS; and the drain of the third PMOS is connected to a drain of a second NMOS, a source of the second NMOS is connected to a drain of a first NMOS, and a source of the first NMOS and a source of the third NMOS.

Abstract: A method includes determining an initial voltage level and duration for an input voltage of a gate of each of multiple transistor devices. Each transistor device receives a power input and controls a current passing through the transistor device. The method also includes controlling the input voltage of the gate of each transistor device according to the initial voltage level and duration. The method further includes receiving real-time feedback including at least one of a present value of the current passing through each transistor device, a present voltage of the power input, and a present value of a capacitor voltage. The method also includes determining, based on the feedback, a subsequent voltage level and duration for the gate of each transistor device. In addition, the method includes controlling the input voltage of the gate of each transistor device according to the determined subsequent voltage level and duration.

Abstract: Devices and methods are provided where a control terminal resistance of a transistor device is set depending on operating conditions within a specified range of operating conditions.

Abstract: A semiconductor device includes a first load terminal, a second load terminal and a semiconductor body coupled to the first load terminal and the second load terminal. The semiconductor body is configured to conduct a load current along a load current path between the first load terminal and the second load terminal. The semiconductor device further includes a control electrode electrically insulated from the semiconductor body and configured to control a part of the load current path, and an electrically floating sensor electrode arranged adjacent to the control electrode. The sensor electrode is electrically insulated from each of the semiconductor body, and the control electrode and is capacitively coupled to the load current path.

Abstract: A semiconductor circuit including a PMOS transistor that includes a first source connected to a power supply, a first drain, and a first gate to which a fixed potential is supplied; an output circuit that outputs a first output signal, which is a reset signal or a power-on signal, and that outputs a second output signal according to a potential of the first drain; a constant current source connected to the first drain; and an NMOS transistor that includes a second source to which a fixed potential is supplied, a second drain connected to the first drain, and a second gate to which the second output signal from the output circuit is applied.

Abstract: A signal generator generates an output signal according to an oscillating signal. The signal generator has a plurality of edge sampling circuits and an edge combining circuit. Each of the edge sampling circuits receives the oscillating signal, samples the oscillating signal to obtain at least one of a rising edge and a falling edge in one cycle of the oscillating signal, and outputs a sampled signal using the at least one of the rising edge and the falling edge. The edge combining circuit combines a plurality of sampled signals generated by the edge sampling circuits, respectively, to generate the output signal.

Abstract: A device for controlling a first control gate transistor, including: a second transistor and a third transistor series-connected between a first and a second terminals of application of a power supply voltage, the junction point of these transistors being connected to the gate of the first transistor; a terminal of application of a digital control signal; a circuit for generating an analog signal according to variations of the power supply voltage; and for each of the second and third transistors, a circuit of selection of a control signal of the first transistor representative of said digital signal or of said analog signal.

Abstract: Some embodiments include apparatuses and methods of using the apparatuses. One of the apparatuses includes a data path to receive data information based on timing of a data capture clock signal, a clock path including a delay circuit to apply a time delay to an input clock signal and generate a delayed clock signal, a clock tree circuit to provide the data capture clock signal and a first feedback clock signal based on the delayed clock signal, a circuitry including latches to sample the input clock signal based on timing of the feedback clock signal and provide sampled information, and a controller to control the delay circuit based on the sampled information in order to cause the data capture clock signal to be out of phase with the input clock signal by one-fourth of a period of the input clock signal.

Abstract: A clamping assembly includes a configuration of mechanically clamped components disposed one on top of the other to form a stack. A clamping device generates a mechanical compressive force on the configuration of the components and a pressure element transmits the mechanical compressive force from the clamping device to the configuration. The pressure element contains a metal foam for a planar, homogeneous transmission of the compressive force. A sub module of a converter having at least one series circuit of power semiconductor switching units implemented as the clamping apparatus is also provided.

Abstract: A control apparatus used in a power transmission system for transmitting power with a magnetic resonance manner to a power reception apparatus from a power transmission apparatus comprises a power control unit configured to control a power transmission state in which transmission power of the power transmission apparatus is controlled in a state in which a power transmission target power reception apparatus is detected, and a test power transmission state in which transmission power of the power transmission apparatus is controlled in a state in which the power transmission target power reception apparatus is not detected.

Abstract: An operation mode determination circuit for sensing a setting resistance between a setting node and a reference voltage or a ground to determine an operation mode, comprises: a pull-up power circuit, for generating a pull-up power onto the setting node, and a floating detection circuit. The pull-up power circuit adjusts the pull-up power at a first power level, and triggers an low power detach detection procedure after a predetermined first time period, wherein the pull-up power is adjusted at a second power level which is less than the first power level to an extent that an electrolysis effect is negligible when an electrolytic substance exists and is coupled to the setting node. The floating detection circuit triggers the operation mode detection procedure when the voltage on the setting node is higher than a first voltage threshold in the low power detach detection procedure.

Abstract: A low power reset circuit includes a bias generator for receiving an operating voltage generated by a power supply and generating a bias voltage in response to the received operating voltage. The operation speed of a shaper for generating a shaped signal for indicating the operating voltage and the operation speed of a comparator for comparing a threshold reference voltage with the shaped signal are both controlled in response to the generated bias voltage. The comparator also generates a comparison signal for indicating a result of the comparison. In response to the comparison signal, a reset signal generator generates a reset signal for resetting protected circuitry powered by the operating voltage generated by the power supply.

Abstract: A gate driver circuit and a method of operating a gate driver circuit. The gate driver circuit comprising a high auxiliary voltage rail and a low auxiliary voltage rail for receiving high auxiliary voltage and low auxiliary voltage, output stage connected to the auxiliary voltage rails and comprising a control input and an output terminal for providing an output voltage of the gate driver, plurality of series connections of controllable switches and resistive components, wherein a first part of the plurality of series connections is connected between the high auxiliary voltage rail and control input of the output stage, and a second part of the plurality of series connections is connected between the low auxiliary voltage rail and control input of the output stage, and a control circuit for controlling the controllable switches for providing a control voltage and a control current to the control input of the output stage.

Abstract: Technology is described for a relative timed clock gated cell. In one example, the relative timed clock gated cell includes a trigger latch and a data clock latch. The trigger latch includes a clock input coupled to a trigger line for transmitting a trigger signal. The trigger latch is configured to generate a data clock signal on an output. The trigger signal is based on a clock signal. The data clock latch includes a clock input coupled to the output of the trigger latch that latches a data input of the data clock latch based on the data clock signal. Various other computing circuitries and methods are also disclosed.

Abstract: An electronic circuit includes a first transistor device and a second transistor device of the same conductivity type. The first transistor device is integrated in a first semiconductor body and includes a first load pad at a first surface of the first semiconductor body and a second load pad at a second surface of the first semiconductor body. The second transistor device is integrated in a second semiconductor body and includes a first load pad at a first surface of the second semiconductor body, and a second load pad at a second surface. The first load pad of the second transistor device is mounted to the first load pad of the first transistor device and the second load pad of the first transistor device is mounted to an electrically conducting carrier.

Abstract: A circuit device includes an oscillation signal generation circuit, a reference signal input terminal to which a reference signal is input, and an internal phase comparator that performs phase comparison between an input signal based on the oscillation signal and the reference signal. The oscillation signal generation circuit generates the oscillation signal using the frequency control data based on a result of the phase comparison from an external phase comparator which performs phase comparison between an input signal based on the oscillation signal and the reference signal in a first mode, and generates the oscillation signal using the frequency control data based on a result of the phase comparison from the internal phase comparator in a second mode.

Abstract: An electrical circuit arranged in a half bridge topology. The electrical circuit includes a high side transistor; a low side transistor; a gate driver and level shifter electrically coupled to a gate of the high side transistor; a gate driver electrically coupled to a gate of the low side transistor; a capacitor electrically coupled in parallel with the gate driver and level shifter; a voltage source electrically coupled to an input of the gate driver and level shifter and an input of the gate driver; and, a bootstrap transistor electrically coupled between the voltage source and the capacitor. A GaN field-effect transistor is synchronously switched with a low side device of the half bridge circuit.