Patents Examined by Dave Mattison
  • Patent number: 10848143
    Abstract: According to one embodiment, there is provided a semiconductor integrated circuit including a first switch transistor, a first reference transistor, a differential amplifier circuit, and a current source. The first switch transistor is electrically connected between a first node on an input terminal side and a second node on an output terminal side. The first reference transistor is electrically connected between the first node and a third node. The differential amplifier circuit has a first input terminal electrically connected to the second node, a second input terminal electrically connected to the third node, and an output terminal electrically connected to a gate of the first switch transistor and a gate of the first reference transistor. The current source is electrically connected between the third node and a reference potential. The first reference transistor has dimensions smaller than dimensions of the first switch transistor.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: November 24, 2020
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Naotaka Koide
  • Patent number: 10840744
    Abstract: An inductive power transmitter comprising: at least one power transmitting coil configured to generate an inductive power transfer (IPT) field; and an object detection system configured to detect objects in or adjacent a space occupied by the IPT field when generated; wherein the object detection system is configured to detect a receiver object based on a tag associated with the receiver object.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: November 17, 2020
    Assignee: Apple Inc.
    Inventor: Ali Abdolkhani
  • Patent number: 10840903
    Abstract: A semiconductor module according to embodiments includes a first external terminal, a second external terminal, a first semiconductor switch which is electrically connected between the first external terminal and the second external terminal and includes a first gate electrode, a second semiconductor switch which is electrically connected in parallel with the first semiconductor switch, between the first external terminal and the second external terminal, and includes a second gate electrode, a first fuse electrically connected between the first external terminal and the first semiconductor switch, and a second fuse electrically connected between the second external terminal and the first semiconductor switch.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: November 17, 2020
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Daisuke Hiratsuka, Nobuto Fujiwara
  • Patent number: 10833664
    Abstract: An apparatus for delaying a signal transition is disclosed. The apparatus includes a first circuit coupled to a first power supply signal and a second, different power supply signal. The first circuit may be configured to, based on a voltage level of a logic signal, sink a current from an intermediate circuit node. A value of the current may be based upon a voltage level of the second different power supply signal. The apparatus also includes a second circuit coupled to the first power supply signal. The second circuit may be configured to generate an output signal based upon a voltage level of the intermediate circuit node. An amount of time between a transition of the logic signal and a corresponding transition of the output signal may be based on an amount of the current.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: November 10, 2020
    Assignee: Apple Inc.
    Inventors: Greg M. Hess, Hemangi U. Gajjewar, Sachmanik Cheema
  • Patent number: 10833674
    Abstract: A switch device including a switch circuit and switch controller. The switch circuit comprises first and second switches to selectively enable a path between an input terminal and an output terminal. The switch controller refers to a selection signal and a switch signal to respectively generate a first switch control signal at a first switch control signal output terminal and a second switch control signal at a second switch control signal output terminal. When the voltage level of an input signal at the input terminal is larger than a power voltage, the switch controller generates the first switch control signal and the second switch control signal capable of turning off the switch circuit. When the voltage level of the input signal is not larger than the power voltage, the switch controller generates the first switch control signal and the second switch control signal according to the switch signal.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: November 10, 2020
    Assignee: Faraday Technology Corp.
    Inventors: Feng Xu, Shu Dong Wu, Zhen Liang Zhang
  • Patent number: 10832915
    Abstract: A semiconductor device, method of manufacture of a semiconductor device, and electronic system are disclosed. For example, the semiconductor device includes at least one trench disposed in a semiconductor substrate of the semiconductor device, wherein the semiconductor substrate has a first conductivity type. The semiconductor device further includes a polysilicon depleted gate shield disposed in the at least one trench, wherein the polysilicon depleted gate shield has a second conductivity type. The semiconductor device also includes a drift region disposed in the semiconductor substrate adjacent to at least one sidewall of the at least one trench, wherein the drift region has the first conductivity type, and a polysilicon gate disposed over the depleted gate shield in the at least one trench.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: November 10, 2020
    Assignee: Great Wall Semiconductor Corporation
    Inventor: Patrick M. Shea
  • Patent number: 10833668
    Abstract: A plurality of lower voltage metal oxide semiconductor sensors are integrated and distributed in various parts of a power MOSFET to provide over temperature protection. The sensors are sensitive to temperatures of the various parts of the power MOSFET and configured to regulate the power MOSFET when a trip temperature is reached by reducing the operation of the MOSFET. A bias network is configured to set the trip temperature. In some configurations, a threshold voltage is used to monitor and control the maximum temperature.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: November 10, 2020
    Assignee: Analog Devices International Unlimited Company
    Inventors: Chiong Yew Lai, Javier A. Salcedo
  • Patent number: 10826489
    Abstract: The present disclosure relates to a structure including a voltage selection circuit which includes a first device and a second device, the voltage selection circuit is configured to output a higher voltage of a first supply voltage and a second supply voltage through one of the first device and the second device, and a voltage difference between the first supply voltage and the second supply voltage is less than a threshold voltage.
    Type: Grant
    Filed: June 6, 2019
    Date of Patent: November 3, 2020
    Assignee: Marvell Asia Pte, Ltd.
    Inventors: Joseph F. Stormes, John A. Fifield, Darren L. Anand
  • Patent number: 10825926
    Abstract: A semiconductor device, method of manufacture of a semiconductor device, and electronic system are disclosed. For example, the semiconductor device includes at least one trench disposed in a semiconductor substrate of the semiconductor device, wherein the semiconductor substrate has a first conductivity type. The semiconductor device further includes a polysilicon depleted gate shield disposed in the at least one trench, wherein the polysilicon depleted gate shield has a second conductivity type. The semiconductor device also includes a drift region disposed in the semiconductor substrate adjacent to at least one sidewall of the at least one trench, wherein the drift region has the first conductivity type, and a polysilicon gate disposed over the depleted gate shield in the at least one trench.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: November 3, 2020
    Assignee: Great Wall Semiconductor Corporation
    Inventor: Patrick M. Shea
  • Patent number: 10819329
    Abstract: The present disclosure relates to a power supply device for a protective relay. The power supply device comprises a power circuit for supplying a power to the control circuit, wherein the power circuit includes: a semiconductor switch element having an input terminal connected to a first node for receiving a direct current, and an output terminal connected to a reference node, wherein the reference node has a voltage lower than a voltage of the first node; and a first voltage drop element disposed between the first node and a second node, wherein the second node is connected to a switching terminal of the semiconductor switch element.
    Type: Grant
    Filed: January 10, 2019
    Date of Patent: October 27, 2020
    Assignee: LSIS CO., LTD.
    Inventor: Young-Joo Lee
  • Patent number: 10819333
    Abstract: A timing controller resetting circuit including: a resistor connected to an output node from which a reset signal is output and a first voltage source which supplies a first voltage; a capacitor connected to the output node and a second voltage source which supplies a second voltage that is lower than the first voltage; a reference voltage source configured to generate a reference voltage that is lower than the first voltage and higher than the second voltage; a comparator including a first input terminal which receives the first voltage, a second input terminal which receives the reference voltage, and an output terminal which outputs a comparison result signal generated by comparing the first voltage with the reference voltage; and a transistor including a first terminal which is connected to the output node, a second terminal which receives the second voltage, and a gate terminal which receives the comparison result signal.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: October 27, 2020
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Ga-Na Kim, Po-Yun Park, Hong-Kyu Kim, Myeongsu Kim, Dongwon Park
  • Patent number: 10812059
    Abstract: A comparator is disclosed, for comparing a first input voltage with a second input voltage and generating a corresponding output voltage. The comparator includes a follower stage coupled to a first supply rail and a second supply rail, a follower stage input terminal for the second input voltage, and a follower stage output terminal. The comparator also includes an inverter stage comprising a first inverter stage supply terminal coupled to the first supply rail, a second inverter stage supply terminal coupled to the follower stage output terminal, an inverter stage input terminal for the first input voltage, and an inverter stage output terminal for providing an inverter stage output voltage having a first range. A signal conditioning means is coupled to the inverter stage output terminal and generates a comparator output voltage at a comparator output terminal having a second range larger than the first range.
    Type: Grant
    Filed: March 5, 2019
    Date of Patent: October 20, 2020
    Assignee: Pragmatic Printing LTD
    Inventor: Joao De Oliveira
  • Patent number: 10804797
    Abstract: The present invention is directed to electrical circuits. According to an embodiment, the present invention provides a charge pump circuit with a bias section and a switch section. The switch section includes a first switch coupled to an early signal and a second switch coupled to a late signal. The charge pump additionally includes a low-pass filter. The switch section includes a first resistor and a second resistor. The first resistor is directly coupled to the first switch and the low-pass filter. The second resistor is directly coupled to the second switch and the first resistor. There are other embodiments as well.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: October 13, 2020
    Assignee: INPHI CORPORATION
    Inventors: Rajasekhar Nagulapalli, Simon Forey, Parmanand Mishra
  • Patent number: 10790805
    Abstract: An impedance converter circuit achieves negative capacitance and/or negative inductance for radio frequency (RF) front end impedance matching for low noise amplifier (LNA) designs. The impedance converter circuit includes a first transistor coupled to a first RF input at a source of the first transistor. The impedance converter circuit also includes a second transistor coupled to a second RF input at a source of the second transistor. The second transistor is cross-coupled to the first transistor to form a cross-coupled pair of transistors. The cross-coupled pair of transistors is configured to generate a negative capacitance or a negative inductance based on a load impedance coupled to a drain of the first transistor and a drain of the second transistor.
    Type: Grant
    Filed: August 9, 2017
    Date of Patent: September 29, 2020
    Assignee: QUALCOMM Incorporated
    Inventor: Makar Snai
  • Patent number: 10790811
    Abstract: A cascaded bootstrapping gate driver configured to provide quick turn-on of a high side power FET and low static current consumption. The cascaded bootstrapping gate driver includes an initial bootstrapping stage with a resistor to decrease static current consumption during transistor turn-off. A secondary bootstrapping stage is driven by the initial bootstrapping stage and includes a GaN FET transistor with a low on resistance in place of the resistor. The source terminal of the GaN FET transistor provides a gate driving voltage to the high side power switch FET. The low on-resistance of the GaN FET transistor provides quick turn-on of the high side power FET. Transistors in the cascaded bootstrapping gate driver are preferably enhancement mode GaN FETs and may be integrated into a single semiconductor die.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: September 29, 2020
    Assignee: Efficient Power Conversion Corporation
    Inventors: Edward Lee, Ravi Ananth, Michael Chapman, Michael A. de Rooij, Robert Beach
  • Patent number: 10778234
    Abstract: A clock generation circuit and a clock signal generation method are disclosed. In the method, a direct current bias circuit in a first clock source superimposes a first direct current voltage on a first clock signal output by a first oscillation circuit, to generate a second clock signal; and a logical operation is performed on the second clock signal and a third clock signal that is generated by a second clock source, to generate a fourth clock signal. The fourth clock signal is used as a signal output by a clock generation circuit. In the method, when the first oscillation circuit cannot normally work, the clock generation circuit can still output a correct clock signal. This avoids clock signal interruption when switching is performed from the first clock source to the second clock source.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: September 15, 2020
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Hua Li, Yan Gao, Sheng Ma
  • Patent number: 10770118
    Abstract: A reverse bias voltage adjuster is provided. The reverse bias voltage adjuster includes an operating voltage generating circuit and a voltage adjusting circuit. The operating voltage generating circuit generates an operating voltage according to a burnin-test signal, a power start signal, and a reverse bias enable signal. In a normal operation mode, the operating voltage is a first voltage value, and in a burnin-test mode, the operating voltage is a second voltage value, wherein the second voltage value is less than the first voltage value. The voltage adjusting circuit is provided with a switch, and in an initial time interval in the burnin-test mode, the voltage adjusting circuit adjusts voltage value of the reverse bias by turning on the switch.
    Type: Grant
    Filed: August 19, 2019
    Date of Patent: September 8, 2020
    Assignee: Winbond Electronics Corp.
    Inventor: Yuji Nakaoka
  • Patent number: 10763827
    Abstract: A delay line includes one or more phase-shifting cells, where each phase-shifting cell includes a high-pass filter circuit that may be selectively coupled to or decoupled from a transmission line. The filter circuit is couplable in parallel with the transmission line and shifts a signal conveyed through the transmission line by a predetermined phase angle. The high-pass filter circuit includes one or more capacitors and one or more reactance elements (e.g., inductors). The selective coupling may be achieved using multi-gate transistors.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: September 1, 2020
    Assignee: NXP B.V.
    Inventor: Henry Andre Christange
  • Patent number: 10753966
    Abstract: A duty cycle measuring circuit, the circuit comprising a synchronizer and a measurer, the synchronizer arranged such that when a signal to be measured comprising pulses having a pulse width and a pulse period is input to the synchronizer, synchronizing signals corresponding to each of pulse rising edge, pulse falling edge, pulse period start and pulse period end are output from the synchronizer, each synchronizing signal comprising a rising or falling edge, wherein the synchronizing signal outputs from the synchronizer are input to the measurer, and wherein the measurer is arranged to provide two measurement outputs based on the synchronizing signal inputs from the synchronizer, the measurement outputs comprising a first measurement output signal indicative of a pulse period measurement of the signal to be measured and a second measurement output signal indicative of a pulse width measurement of the signal to be measured.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: August 25, 2020
    Assignee: SEQUANS COMMUNICATIONS S.A.
    Inventors: Martin Wiezell, Ali Reza Bastami
  • Patent number: 10756718
    Abstract: A gate driving apparatus for a power semiconductor device may include: a first off-resistor and a second off-resistor each having a first end connected to a gate of the power semiconductor device; a first off-switch configured to determine a connection state between a second end of the first off-resistor and a ground based on a gate driving signal for determining an on/off state of the power semiconductor device; a second off-switch configured to determine a connection state between a second end of the second off-resistor and the ground; an electric current detector configured to detect an electric current flowing from a collector (drain) of the power semiconductor device to an emitter (source) of the power semiconductor device; and a controller configured to determine an open/closed state of the second off-switch based on the gate driving signal and a magnitude of the electric current detected by the electric current detector.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: August 25, 2020
    Assignees: Hyundai Motor Company, Kia Motors Corporation
    Inventors: Ki Jong Lee, Ji Woong Jang, Kang Ho Jeong, Sang Cheol Shin, Han Geun Jang