Abstract: A burn-in resilient integrated circuit is provided. The burn-in resilient integrated circuit includes an inverter chain and a plurality of inverter circuits on the inverter chain. The burn-in resilient integrated circuit also includes a loop providing an electrical connection from an output of the inverter chain to an input of the inverter chain. The loop is selectable in accordance with a burn-in operation.

Abstract: Systems and techniques are described for providing control of a monitoring system. In some implementations, a monitoring device is located in a building and is configured to monitor at least a portion of the building based on output from one or more sensors. A monitoring server is located remote from the building and is configured to communicate with the monitoring device. The monitoring server may be configured to translate one or more parameters received from a client device into an interpreted monitoring script and a trigger that causes performance of the interpreted monitoring script. The monitoring device may include an interpreter configured to determine that the trigger has been met and initiate performance of the interpreted monitoring script to evaluate a monitoring rule in accordance with one or more configurable parameters.

Abstract: It is desirable to reduce power consumption without reducing a function in an electronic apparatus operating in a plurality of modes different in power consumption from one another. A processor operates in a normal mode, in which power consumption is higher, of two modes different in power consumption from each other, and stops operation in a power saving mode, in which the power consumption is lower, of the two modes. A control section outputs a power saving mode control command instructing an increase or decrease of a supply electric power to a digital circuit different from the processor in the power saving mode. A power source managing integrated circuit increases or decreases the supply electric power to the digital circuit in accordance with the power saving mode control command, and outputs the increased or decreased supply electric power.

Abstract: A method includes in a switching cycle of a power converter in a wireless power transfer system, finding a time instant corresponding to one fourth of the switching cycle, wherein the power converter is coupled between an input power source and a transmitter coil magnetically coupled to a receiver coil, at the time instant, detecting a current flowing through the transmitter coil, wherein power transferred between the transmitter coil and the receiver coil is proportional to the current flowing through the transmitter coil, comparing the current flowing through the transmitter coil with a plurality of predetermined thresholds to determine whether a transient occurs, and applying a control mechanism to the power converter in response to an occurrence of the transient.

Abstract: Power electronic module comprising a plurality of semiconductor power electronic components electrically connected to an electrical support, and a cooling device in thermal contact with each component, each component being present between the electrical support and the cooling device and being mounted on the electrical support via at least one electrically conductive spring element.

Abstract: A limiter having a more ideal limiting function, a short response time, and an adjustable limiting threshold. In one embodiment, a self-activating limiter stack is coupled between circuit ground and a signal line between a source and a receiver. The limiter stack limits the power from the source when the voltage on the signal line exceeds the breakdown voltage of the limiter stack. The threshold of the limiter stack is controlled in part by a first control voltage applied to a control input. A rectifying power detector circuit connected between a node on the signal line and the control input of the limiter stack provides a second control voltage as a function of the signal power at the node. The combined first and second control voltages are applied to the control input to modulate the ON resistance of the limiter stack, thereby limiting the leakage power reaching the protected receiver.

Abstract: A power control circuit according to one embodiment includes an H-bridge circuit formed using a plurality of power transistors. The power transistors are respectively connected to current measurement circuits that measure currents flowing through the power transistors. Each of the power transistors includes a main emitter and a sense emitter through which a current corresponding to a current flowing through the main emitter flows. Each of the current measurement circuits measures a current flowing through each of the power transistors by using a current flowing through the sense emitter included in the power transistor. A control circuit controls the power transistors based on current values respectively measured by the current measurement circuits.

Abstract: A power supply system includes a current driver circuit, a sensor circuit, a control circuit, a voltage generator circuit and a signal generator circuit. The current driver circuit generates, based on a pulse signal, an output current for driving a load unit that includes series connected loads. The sensor circuit senses the output current to generate a sensed voltage. For each load, the control circuit is operable, based on a control input, to allow or not to allow the output current to flow through the load. The voltage generator circuit generates a reference voltage based on the control input. The signal generator circuit generates the pulse signal based on the reference voltage and the sensed voltage.

Abstract: A processing element for implementation in a digital signal processing system is provided. The processing element is configured to receive a first data stream comprising a plurality of digital values where each value represents a sample of an analog signal. The processing element is further configured to receive a second data stream comprising a series of digital values where each value represents a sample of the analog signal. The processing element is configured to filter the first data stream via a first Farrow-structured fractional delay (FD) filter and output a filtered first data stream; filter the second data stream via a second Farrow-structured FD filter and output a filtered second data stream; and temporarily store values from the second data stream and output the stored values to the first Farrow-structured FD filter so that the stored values can be used to filter the first data stream.

Abstract: A drive-sense circuit includes a signal source circuit and a signal change detection circuit. The signal source circuit is operably coupled to a sensor. When enabled, the signal source circuit provides a signal to the sensor. When the sensor is exposed to a condition, an electrical characteristic of the sensor affects the signal, which includes a DC component and/or an oscillating component. When enabled, the signal change detection circuit is operably coupled to detect an effect on the signal as a result of the electrical characteristic of the sensor. The signal change detection circuit is further operable to generate a signal representative of change to the signal based on the detected effect on the signal.

Abstract: The switch circuit includes a MOS transistor one end of which is coupled to a power supply line and to a control terminal of which voltage is input, a switch coupled between the power supply line and one end of the MOS transistor or one end of which is coupled to the other end of the MOS transistor, a MOS transistor coupled between an output terminal and ground potential, and a series-connected switch and constant current source coupled to a connection point between an opposite-side end of the whole series-connected MOS transistor and switch to the power supply line and the control terminal of the MOS transistor and performing adjustment to prevent current from flowing from the MOS transistor to ground potential after the switch turns on until the MOS transistor turns on.

Abstract: A semiconductor device having a power source terminal, a ground terminal, an input terminal, an output terminal and a status output terminal. The semiconductor device includes a power semiconductor switch connected between the power source terminal and the output terminal, a logic circuit connected to the power semiconductor switch, and a ground terminal opening detection circuit connected to the ground terminal and the status output terminal. The logic circuit is configured to generate, according to a signal inputted to the input terminal, an output logic signal for turning on or off the power semiconductor switch. The ground terminal opening detection circuit is configured to detect a state in which the ground terminal is opened, based on a rise in a potential of the ground terminal, and to output, via the status output terminal, a detection signal in response to the detection of the state.

Abstract: In an embodiment, a digital output driver circuit comprises an output stage having first and second transistors. A drive stage is configured to drive control terminals of the first and second transistors and comprising switching circuitry and current generator circuitry. In a first configuration, the driver circuit is configured to connect a control terminal of the second transistor to the reference node to turn off the second transistor; and connect a first capacitance to the current generator circuitry and to a control terminal of the first transistor to turn on the first transistor. In a second configuration, the driver circuit is configured to turn off the first transistor and connect the control terminal of the second transistor to the current generator circuitry and to the second capacitance to turn on the second transistor.

Abstract: A filter circuit includes a first rise delay circuit that delays a rising time of a first shifted signal by a predetermined time for output and a first fall delay circuit that delays a falling time of a second shifted signal by a predetermined time for output. The first rise delay circuit is configured so that a second rise delay signal does not follow a change in a first voltage toward a decreasing side and follows a change in the first voltage toward an increasing side. The first fall delay circuit is configured so that a second fall delay signal does not follow a change in the first voltage toward a decreasing side and follows a change in the first voltage toward an increasing side.

Abstract: A gate driver for driving a gate of a switching element in accordance with an input signal is provided. The gate driver is configured to change a gate driving condition in accordance with a detected value of power supply voltage. Each time when the switching element is turned off, the gate driver stores a time width from a time when the input signal is switched to an off command to a time when switch-off surge occurs in the switching device. If it is determined that the gate driving condition should be changed during turn-off operation of the switching element, the gate driver switches the gate driving condition when a time corresponding to the time width stored at a previous turn-off is elapsed after a current turn-off of the switching element is started.

Abstract: An enhancement mode GaN FET based gate driver circuit including an active pre-driver to drive a high-slew rate, high current output stage GaN FET. Due to the active driver current from the pre-driver, the output stage pull-up FET can turn on faster as compared to a pre-driver that utilizes a passive pull-up load. The active pre-driver must provide a voltage to drive the gate of the output stage pull-up FET which is higher than the normal supply voltage to enable the maximum output level of the driver FET to approach the normal supply voltage. A feedback circuit is included in the active pre-driver to avoid the need for two supply voltages.

Abstract: An RF energy harvesting apparatus comprising an energy harvesting antenna carried on a substrate for fixing the antenna to an electrical device, wherein the antenna comprises a coil of conductive material carried on the substrate, wherein the coil provides two loops of conductive material on the substrate, the coil comprising a second loop inside a first loop; and wherein the coil comprises at least one segment arranged to reduce spatial variations in the H-field in an area circumscribed by the first loop.

Abstract: A semiconductor integrated circuit includes a first signal transmission path and a second signal transmission path in parallel with each other, a first variable delay circuit provided on the first signal transmission path and configured to cause a first signal to be delayed by a first delay amount, a duty adjustment circuit provided on the first signal transmission path in series with the first variable delay circuit, and a second variable delay circuit provided on the second signal transmission path and configured to cause a second signal to be delayed by a second delay amount. The first delay amount is smaller than the second delay amount by a third delay amount corresponding to an amount of delay applied to the first signal by the duty adjustment circuit.

Abstract: A filter includes a filter circuit, a first processing circuit, and a second processing circuit. The filter circuit receives an input signal from an input node of the filter, and converts the input signal into a voltage output. The first processing circuit provides a first control voltage to an output node of the filter according to the voltage output, wherein the first control voltage is derived from an alternating current (AC) component of the voltage output. The second processing circuit provides a second control voltage to the output node of the filter according to the voltage output, wherein the second control voltage is derived from applying DC level shift to a direct current (DC) component of the voltage output.

Abstract: Circuits and methods for delay mismatch compensation are described. A circuit may comprise multiple data paths between a signal source, such as a driver, and a load. The paths may have different lengths, thus causing delay mismatches. An exemplary circuit of the type described herein may comprise delay elements and at least one feedback circuit designed to compensate for such delay mismatches. The circuit may operate in different phases, such as a compensation phase and a driving phase. In the compensation phase, rings oscillators including delay elements and the at least one feedback circuit may be formed. In this phase the delay may be adjusted to compensate for mismatches. In the driving phase, the signal source may be connected to the load.