Abstract: A level-shifting circuit includes a first supply terminal configured to receive a first supply voltage, a second supply terminal configured to receive a second supply voltage different from the first supply voltage, an input terminal of the level-shifting circuit configured to receive a voltage having a first voltage level, and an output terminal of the level-shifting circuit. The level-shifting circuit can include a shifting circuit having electrical connections to the input terminal and the output terminal and configured to, in response to a first voltage at a first node, produce a second voltage at a second node. The level-shifting circuit can also include a feedback circuit and a clamping circuit configured to limit leakage current.

Abstract: A wide-band digital buffer formed in a III-V substrate including a first transistor, a second transistor, a pull-up circuit shifts a t signal to a level of the first transistor. A first capacitor receives the signal, and passes at least a portion of the AC component of the signal to the first transistor. A resistor receives a first bias voltage, and passes it to the first transistor. A pull-down circuit shifts a second signal to a level of the second transistor. A second capacitor receives the second signal, and passes at least a portion of the AC component of the second signal to the second transistor. A second resistor receives a second bias voltage, and passes it to the second transistor.

Abstract: Described herein are configurations for an integrated resonator-shield structure for wireless power transfer. In embodiments a conductor shield is used to shield the resonator from perturbing objects. In embodiments the conductor shield is used for a current return path for the conductors of the resonator. The resonator shield can be divided into separate conductor segments to tailor the current distributions in the conductor shield.

Abstract: A back bias voltage generator circuit includes a first resistive element connected in series with a second resistive element; a first amplifier having a first input coupled to an input voltage, a second input coupled to a first node at a first terminal of the first resistive element, and an output coupled to an N-polarity metal-oxide semiconductor (NMOS) bias voltage node. A second amplifier has a first input coupled to a symmetrical voltage, a second input coupled to a second node between a second terminal of the first resistive element and a first terminal of the second resistive element, and an output coupled to a P-polarity metal-oxide semiconductor (PMOS) bias voltage node and the second terminal of the second resistive element. The symmetrical voltage is between a highest supply voltage and a lowest supply voltage coupled to the first amplifier.

Abstract: A semiconductor device may include a divider circuit and a detection circuit. The divider circuit may divide an external clock to generate a plurality of divided clocks. The detection circuit may generate a phase information signal and a timing information signal based on a plurality of data determination signals and the plurality of divided clocks.

Abstract: The disclosure relates to a control device for controlling a load, wherein the control device comprises the following elements: a first current control valve between a first port of the load and a first potential of an operating voltage; a second current control valve between a second port of the load and a second potential of the operating voltage; a processor configured to actuate the second current control valve when the first current control valve is closed, in order to control a current through the load; and a sampling device for determining an input voltage through the first current control valve, wherein the processor is configured to determine the presence of a short circuit between the first port and the first potential if the input voltage does not increase when the first current control valve is opened gradually.

Abstract: Systems and techniques are described for providing control of a monitoring system. In some implementations, a monitoring device is located in a building and is configured to monitor at least a portion of the building based on output from one or more sensors. A monitoring server is located remote from the building and is configured to communicate with the monitoring device. The monitoring server may be configured to translate one or more parameters received from a client device into an interpreted monitoring script and a trigger that causes performance of the interpreted monitoring script. The monitoring device may include an interpreter configured to determine that the trigger has been met and initiate performance of the interpreted monitoring script to evaluate a monitoring rule in accordance with one or more configurable parameters.

Abstract: A circuit includes a sensor configured to receive an input signal and to provide a sensor output signal in response to the received input signal. A plurality of mirror circuits are configured to receive the sensor output signal from the sensor and to generate mirror circuit output signals. The plurality of mirror circuits includes a first mirror circuit and at least a second mirror circuit. The first mirror circuit increases its respective mirror circuit output signal until its saturation value is reached. The second mirror circuit increases its respective mirror output signal if the sensor output signal is above a threshold value and until its saturation value is reached.

Abstract: A transmission circuit includes: a clock generating circuit configured to generate a first clock signal and a second clock signal whose frequency is lower than a frequency of the first clock signal; a first conversion circuit configured to convert, based on the second clock signal, input data into intermediate data whose bit width is narrower than a bit width of the input data; a second conversion circuit configured to convert, based on the first clock signal, the intermediate data into output data whose bit width is narrower than the bit width of the intermediate data; capture circuits configured to sequentially capture a data sequence of the output data; an analysis circuit configured to perform an analysis on the captured data sequence; and a phase adjusting circuit configured to adjust a phase of the second clock signal based on a result of the analysis.

Abstract: An RF switch includes two or more coupled RF switch cells, each RF switch cell including a transistor having a first source/drain node, a second source/drain node, and a gate node, a first varactor is coupled between the first source/drain node and the gate node, and a second varactor is coupled between the second source/drain node and the gate node.

Abstract: A method of inductive power transmission by a transmitter and a receiver of an electrically operated device, the transmitter having at least one transmitter coil and the receiver having at least one receiver coil, a control for the power to be transmitted is provided in the transmitter, a minimum power is transmitted by the transmitter through the control at the start of a power transmission, the minimum transferring power is sufficiently dimensioned to activate a controller of the receiver of the electrically operated device. By influencing the field of the transmitter coil, the controller supplies data packets to the control that contain information about the electrically operated device so that an optimal power adapted to the power class of the device is transmitted by the transmitter.

Abstract: An electronic device includes at least one electronic component, a gradient heat-flux sensor GHFS based on thermoelectric anisotropy and conducting heat generated by the electronic component, and a controller adapted to manage electrical current of the electronic component at least partly on the basis of an electrical control signal generated by the gradient heat-flux sensor and proportional to a heat-flux through the gradient heat-flux sensor. Therefore, the electrical current and thereby also the heat generation of the electronic component are managed directly on the basis of the heat-flux generated by the electronic component. Thus, the electrical current can be managed without a need for voltage and current measurements which may be challenging to be carried out with a sufficient bandwidth especially when the switching frequency of the electronic component is on a range from hundreds of kHz to few MHz.

Abstract: A phase lock loop (PLL) circuit includes a selection mode device before a phase detector and time-to-digital converter (TDC). In a first mode, the selection mode device outputs two signals having consecutive rising edges that are spaced apart in time by substantially one period of the reference clock signal. In a second mode, the selection mode device outputs two signals having consecutive rising edges that are spaced apart in time by substantially one period of the feedback clock signal. In a third mode, the selection mode device outputs the reference and feedback clock signals. The phase detector and TDC are configured to generate a signal: indicating the reference clock frequency in the first mode; indicating of the feedback clock frequency in the second mode; and indicating a phase/frequency difference between the feedback and reference clocks in the third mode. These signals are used to control a VCO clock signal.

Abstract: A calculation code generation circuit performs calibration using a counter, and a digital correction circuit including the same. The calculation code generation circuit performs a calculation process according to first and second modes, the calculation process including generating a first code by sampling a first value of the count code, generating a second code by sampling a second value of the count code, generating first and second calculation codes using the first and second codes in the first and second modes, respectively, and generating, in a calibration disable state, a third calculation code using the first and second calculation codes generated in the first and second modes, respectively, to remove the influence of the comparison offset or comparison performance of a comparator, thereby removing a calibration error.

Abstract: A method for controlling voltage of a doped well in a substrate is provided. The substrate and the doped well are in different conductive type. The method includes applying a substrate voltage to the substrate while a well power for applying a well voltage to the doped well is turned off. The method also includes detecting a voltage level of one of the doped well and the substrate to judge whether or not a voltage target is reached. The well power is turned on to apply the well voltage to the doped well when the voltage level as detected reaches to the voltage target.

Abstract: In some implementations, a system includes a phase locked loop (PLL) circuit and a digital control unit. The PLL circuit includes a digital loop filter, a digitally controlled oscillator (DCO), and a divider circuit. The digital control unit is configured determine a preset value for the DCO; determine initial gain coefficients and final gain coefficients for the digital loop filter; determine N/R values for the divider circuit; while the PLL circuit is operating in an open-loop configuration, provide the preset value to the DCO, the initial gain coefficients to the digital loop filter, and the N/R values to the divider circuit; after providing the preset value, initial gain coefficients, and N/R values, initiate operation of the PLL circuit in the closed-loop configuration; and in response to detection of a phase lock of the PLL circuit operating in the closed-loop configuration, provide the final gain coefficients to the digital loop filter.

Abstract: Methods and devices are discussed where a plurality of input signals having different phases are provided. From the input signals, a plurality of signal pairs are selected, and intermediate signals are generated based on the signal pairs. The intermediate signals are then combined.

Abstract: Quantum circuits and associated methods use Repeat-Until-Success (RUS) circuits to perform approximate multiplication and approximate squaring of input values supplied as rotations encoded on ancilla qubits. So-called gearbox and programmable ancilla circuits are coupled to encode even or odd products of input values as a rotation of a target qubit. In other examples, quantum RUS circuits provide target qubit rotations that are associated with reciprocals using series expansion representations.

Abstract: A counter includes: a computing module (100) and N counting modules (101). Each counting module includes a plurality of counting spaces corresponding to different counting entries, and counting spaces of the same counting entry in different counting modules have the same address, wherein the counting module is arranged to provide a value for computing to the computing module in response to a counting application of a counting application source. The computing module is arranged to read values of the same counting entry in different counting modules and accumulate the read values to obtain a total count value of the counting entry, N being an integer not less than 1. Also disclosed is a counting method.

Abstract: A comparator includes a first voltage-time conversion circuit, a second voltage-time conversion circuit, and a determination circuit. A first delay unit includes a first falling edge delay circuit that delays a falling edge based on a first input signal, a first rising edge delay circuit that delays a rising edge based on a second input signal, and a first output circuit. A second delay unit includes a second falling edge delay circuit that delays a falling edge based on the second input signal, a second rising edge delay circuit that delays a rising edge based on the first input signal, and a second output circuit.