Abstract: A semiconductor device structure and method of manufacturing a semiconductor device. The semiconductor device may comprise a semiconductor die having a top major surface that has one or more electrical contacts formed thereon, an opposing bottom major surface, and side surfaces; a molding material encapsulating the top major surface, the bottom major surface and the side surfaces of the semiconductor die, wherein the molding material defines a package body that has a top surface and a side surface; wherein the plurality of electrical contacts are exposed on the top surface of the package body and a metal layer is arranged over and electrically connected to the electrical contacts and wherein the metal layer extends to and at least partially covers a side surface of the package body.

Abstract: A semiconductor structure is disclosed, which comprises a substrate, a bit line (BL) stack feature and a BL spacer. The substrate has a cell area and a periphery area defined thereon. The bit line stack feature formed over an active region in the cell area, comprises a buffer liner having a U-shaped profile that opens upwardly in a cross section thereof and defining an inner surface, a BL conductor disposed in the U-shaped profile on the inner surface, and a capping layer over the BL conductor. The BL spacer covers sidewall surfaces of the BL stack feature.

Abstract: The present disclosure relates to the field of display technologies, and provides a display substrate, a manufacturing method thereof, a corresponding display panel and an encapsulation method for the same. The display substrate includes a base plate comprising a display area and an encapsulation area surrounding the display area, and an insulating layer and a plurality of wires located on the base plate. The insulating layer comprises at least one groove in the encapsulation area. At least one of the plurality of wires comprises a first portion in the display area and a second portion within a corresponding groove of the encapsulation area. There is only one said second portion present in each groove.

Abstract: A semiconductor interconnect structure and its manufacturing method are presented. The manufacturing method includes: providing a substrate structure, wherein the substrate structure comprises: a substrate; a first metal layer on the substrate; a dielectric layer on the substrate, wherein the dielectric layer covers the first metal layer, and wherein the dielectric layer has a hole extending to the first metal layer; and a hard mask layer on the dielectric layer; removing the hard mask layer on the dielectric layer; selectively depositing a second metal layer at the bottom of the hole; and depositing a third metal layer, wherein the third metal layer fills the hole. This semiconductor interconnect structure provides improved reliability over conventional structures.

Abstract: A package for power electronics includes a power substrate, a number of power semiconductor die, and a Kelvin connection contact. Each one of the power semiconductor die are on the power substrate and include a first power switching pad, a second power switching pad, a control pad, a semiconductor structure, and a Kelvin connection pad. The semiconductor structure is between the first power switching pad, the second power switching pad, and the control pad, and is configured such that a resistance of a power switching path between the first power switching pad and the second power switching pad is based on a control signal provided at the control pad. The Kelvin connection pad is coupled to the power switching path. The Kelvin connection contact is coupled to the Kelvin connection pad of each one of the power semiconductor die via a Kelvin conductive trace on the power substrate.

Abstract: A semiconductor device assembly includes a substrate and a die coupled to the substrate, the die including a first contact pad electrically coupled to a first circuit on the die including an active circuit element, a first TSV electrically coupling the first contact pad to a first backside contact pad, and a second contact pad electrically coupled to a second circuit including only passive circuit elements. The substrate includes a substrate contact electrically coupled to the first and second contact pads. The assembly can further include a second die including a third contact pad electrically coupled to a third circuit including a second active circuit element, and a fourth contact pad electrically coupled to a fourth circuit on the second die including only passive circuit elements. The substrate contact can be electrically coupled to the third contact pad, but electrically disconnected from the fourth contact pad.

Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a semiconductor die surrounded by a first molding compound layer. A redistribution layer (RDL) structure is formed on a non-active surface of the semiconductor die and the first molding compound layer. A second molding compound layer is formed on the RDL structure. An insulating capping layer covers the second molding compound layer. An antenna is electrically coupled to the semiconductor die and includes a first antenna element formed in the RDL structure and a second antenna element formed between the second molding compound layer and the insulating capping layer.

Abstract: Presented herein is a WLCSP intermediate structure and method forming the same, the method comprising forming a first redistribution layer (RDL) on a carrier, the first RDL having mounting pads disposed on the first RDL, and mounting interposer dies on a second side of the first RDL. A second RDL is formed over a second side of the interposer dies, the second RDL having a first side adjacent to the interposer dies, one or more lands disposed on the second RDL, at least one of the one or more lands in electrical contact with at least one of the interposer dies or at least one of the mounting pads. A molding compound is formed around the interposer dies and over a portion of the first RDL prior to the forming the second RDL and the second RDL is formed over at least a portion of the molding compound.

Abstract: The present disclosure discloses a display substrate and a manufacturing thereof. The display substrate comprises a base substrate, a pixel defining layer formed on the base substrate, wherein the pixel defining layer is provided with an opening region comprising a bottom wall and at least one sidewall, wherein in the opening region, an edge of the bottom wall is provided with at least one hydrophilic inducing column, wherein at least one of the hydrophilic inducing column has a hydrophilic surface.

Abstract: An active matrix substrate in which step-caused disconnection of a metal film in a contact hole does not easily occur includes a first to third insulating films and first to third metal films on a glass substrate and a contact hole electrically connecting the first and second metal film, the contact hole including first to third hole present respectively in the first to third insulating films, the first and third metal films being in contact with each other inside the first hole, the second insulating film and an oxide semiconductor film overlapping with each other in a region below the third hole, the second and third metal films being in contact with each other in a region above the first insulating film and either inside or below the third hole.

Abstract: [Problem] To bond an electronic component on a substrate via an adhesive material satisfactorily. [Solution] A bonding device 10 for thermally bonding an electronic component 100 to a substrate 110 or to another electronic component via an adhesive material 112, the bonding device being provided with: a bonding tool 40 comprising a bonding distal-end portion 42 which includes a bonding surface 44 and tapered side surfaces 46 formed in a tapering shape becoming narrower toward the bonding surface 44, the bonding surface 44 having a first suction hole 50 for suction-attaching the electronic component 100 via an individual piece of a porous sheet 130, the tapered side surfaces 46 having second suction holes 52, 54 for suction-attaching the porous sheet 130; and a bonding control unit 30 which controls the first suction hole 50 and the second suction holes 52, 54 independently from each other.

Abstract: A semiconductor device has a semiconductor package and an interposer disposed over the semiconductor package. The semiconductor package has a first semiconductor die and a modular interconnect unit disposed in a peripheral region around the first semiconductor die. A second semiconductor die is disposed over the interposer opposite the semiconductor package. An interconnect structure is formed between the interposer and the modular interconnect unit. The interconnect structure is a conductive pillar or stud bump. The modular interconnect unit has a core substrate and a plurality of vertical interconnects formed through the core substrate. A build-up interconnect structure is formed over the first semiconductor die and modular interconnect unit. The vertical interconnects of the modular interconnect unit are exposed by laser direct ablation. An underfill is deposited between the interposer and semiconductor package.

Abstract: An applying method includes the following steps. Firstly, a conductive adhesive including a plurality of conductive particles and an insulating binder is provided. Then, a carrier plate is provided. Then, a patterned adhesive is formed on the carrier plate by the conductive adhesive, wherein the patterned adhesive includes a first transferring portion. Then, a manufacturing device including a needle is provided. Then, the needle of the manufacturing device is moved to contact the first transferring portion. Then, the transferring portion is transferred to a board by the manufacturing device.

Abstract: A microelectronic device has bump bond structures on input/output (I/O) pads. The bump bond structures include copper-containing pillars, a barrier layer including cobalt and zinc on the copper-containing pillars, and tin-containing solder on the barrier layer. The barrier layer includes 0.1 weight percent to 50 weight percent cobalt and an amount of zinc equivalent to a layer of pure zinc 0.05 microns to 0.5 microns thick. A lead frame has a copper-containing member with a similar barrier layer in an area for a solder joint. Methods of forming the microelectronic device are disclosed.

Abstract: Semiconductor devices having interconnects incorporating negative expansion (NTE) materials are disclosed herein. In one embodiment a semiconductor device includes a substrate having an opening that extends at least partially through the substrate. A conductive material having a positive coefficient of thermal expansion (CTE) partially fills the opening. A negative thermal expansion (NTE) having a negative CTE also partially fills the opening. In one embodiment, the conductive material includes copper and the NTE material includes zirconium tungstate.

Abstract: A hard macro includes a periphery defining a hard macro area and having a top and a bottom and a hard macro thickness from the top to the bottom, the hard macro including a plurality of vias extending through the hard macro thickness from the top to the bottom. Also an integrated circuit having a top layer, a bottom layer and at least one middle layer, the top layer including a top layer conductive trace, the middle layer including a hard macro and the bottom layer including a bottom layer conductive trace, wherein the top layer conductive trace is connected to the bottom layer conductive trace by a via extending through the hard macro.

Abstract: The present disclosure provides a method of forming an integrated circuit structure. The method includes depositing a first metal layer on a semiconductor substrate; forming a hard mask on the first metal layer; patterning the first metal layer to form first metal features using the hard mask as an etch mask; depositing a dielectric layer of a first dielectric material on the first metal features and in gaps among the first metal features; performing a chemical mechanical polishing (CMP) process to both the dielectric layer and the hard mask; removing the hard mask, thereby having portions of the dielectric layer extruded above the metal features; forming an inter-layer dielectric (ILD) layer of the second dielectric material different from the first dielectric material; and patterning the ILD layer to form openings that expose the first metal features and are constrained to be self-aligned with the first metal features by the extruded portions of the first dielectric layer.

Abstract: Techniques and mechanisms for providing at a packaged device an integrated circuit (IC) chip and a chiplet, wherein memory resources of the chiplet are accessible by a processor core of the IC chip. In an embodiment, a hardware interface of the packaged device includes first conductive contacts at a side of the chiplet, wherein second conductive contacts of the hardware interface are electrically interconnected to the IC chip each via a respective path which is independent of the chiplet. In another embodiment, one or more of the first conductive contacts are configured to deliver power, or communicate a signal, to a device layer of one of the IC chip or the chiplet.

Abstract: A method of providing a sensor IC package can include applying a film to a leadframe having first and second surfaces, mounting at least one component to the film, and applying a pre-mold material to cover at least a portion of the leadframe and the passive component while leaving a first side of the leadframe exposed. The film can be removed and a die attached to the first side of the leadframe. At least one electrical connection can be formed between the die and the leadframe. The assembly of the die, the leadframe, and the pre-mold material can be encapsulated with a final mold material to provide a low profile IC package.

Abstract: A semiconductor device includes a conductive line and a conductive via contacting the conductive line. A first dielectric material contacts a first sidewall surface of the conductive via. A second dielectric material contacts a second sidewall surface of the conductive via. The first dielectric material includes a first material composition, and the second dielectric material includes a second material composition different than the first material composition.