Abstract: A method for forming a contact opening is described and which includes providing a node location to which electrical connection is to be made; forming a conductive line adjacent the node location, the conductive line having a conductive top and sidewall surfaces; forming electrically insulative oxide in covering relation relative to the top surface of the conductive line; forming electrically insulative nitride sidewall spacers over the conductive sidewall surfaces, the nitride sidewall spacers projecting outwardly of the conductive line top conductive surface, the electrically insulative oxide positioned between the nitride sidewall spacers; forming an electrically insulative layer outwardly of the conductive line, and the node location; and etching a contact opening to the node location or the top surface through the electrically insulative layer substantially selective relative to the nitride sidewall spacers.

Abstract: A capacitor for high density DRAM applications comprises a high-∈ capacitor dielectric such as BST or PZT in an arrangement which obviates the need for barrier layers during fabrication. The fabrication process allows for electrode placement by simple sputter deposition and further provides for the possibility of capacitor spacing below that of conventional lithographic techniques.

Abstract: A memory cell provides point defect trap sites in an insulator for storing data charges. Single electrons are stored on respective point defect trap sites and a resulting parameter, such as transistor drain current, is detected. By adjusting the density of the point defect trap sites, more uniform step changes in drain current are obtained as single electrons are stored on or removed from respective trap sites. By also adjusting the trapping energy of the point defect trap sites, the memory cell provides either volatile data storage, similar to a dynamic random access memory (DRAM), or nonvolatile data storage, similar to an electrically erasable and programmable read only memory (EEPROM). The memory cell is used for storing binary or multi-state data.

Abstract: A split-gate MOS transistor includes two separate but partially overlapping gates to reduce the electric field near the drain-channel interface region and, thereby, has an increased gated-diode breakdown voltage.

Abstract: An integrated circuit transistor and method of making the same are provided. The transistor includes a substrate, first and second source/drain regions, and a gate electrode stack coupled to the substrate. The gate electrode stack is fabricated by forming a first insulating layer on the substrate, forming a first conductor layer on the first insulating layer, and forming a metal layer on the first conductor layer. A second insulating layer, such as an interlevel dielectric layer, is coupled to the substrate adjacent to the gate electrode stack. Sidewall spacers and LDD processing may be incorporated. The transistor and method integrate metal and polysilicon into a self-aligned gate electrode stack.

Abstract: In a peripheral circuit region requiring a conductive path between layers at the periphery of a memory cell array region, a conductive path is provided, after removing a silicon nitride film used for self-alignment contact from the area of the contacting portion of a conductor, by forming an interlayer oxide film on the conductor and providing an opening through the interlayer oxide film. Alternatively, a conductive path is provided, after forming the interlayer oxide film on the silicon nitride film used for self-alignment contact, by forming an opening throughout the interlayer oxide film and silicon nitride film.

Abstract: Linear integrated circuit capacitors having greater capacitance per unit area by using lateral flux. One embodiment comprises a two metal layer capacitor wherein each metal layer is comprised of two capacitor conductive components. The capacitor conductive components are cross-coupled so that the total capacitance is the sum of the vertical flux between the metal layers, and the lateral flux along the edges between the two capacitor conductive components in each of the metal layers. The lateral flux between the capacitor conductive components in a single metal layer increases the capacitance per unit area and decreases the bottom-plate parasitic capacitance. Increasing the length of the common edge formed by capacitor conductive components in a metal layer increases the capacitance per unit area. In one lateral flux capacitor, each metal layer is comprised of a plurality of rows, alternate rows are coupled together such that lateral flux is generated between each of the rows.

Abstract: To reduce threshold levels in fully depleted SOI devices having back gate wells, the channel regions of the devices are formed of an intrinsic or pseudo-intrinsic semiconductor. Also, multiple well structures or isolation regions are formed below the oxide layer to reduce diode junction leakage between the back gate wells of the devices.

Abstract: In an HEMT, a channel forming layer is arranged above a semi-insulating substrate via a buffer layer. A spacer layer is arranged on the channel forming layer and an electron supplying layer and a Schottky contact layer are sequentially arranged on the spacer layer. A diffusion preventing layer, for preventing a metal element of a gate electrode from diffusing into the channel forming layer, is arranged in the Schottky contact layer.

Abstract: In a substrate, a device hole is punched, and a metal wiring pattern is formed on the substrate. Then, an insulating film is formed from the side of the metal wiring pattern so as to cover at least the device hole. In this state, the insulating film is formed for fixing the inner leads of the metal wiring pattern, which are projected on the device hole. Then, the semiconductor chip is provided so as to face the device hole from the side of the substrate, and the electrode is connected to the inner leads via the ACF by thermocompression. The described arrangement is provided so as to realize an extremely narrow frame in a liquid crystal module. According to the described method, a quality TCP semiconductor device can be manufactured in a simple manner at high yield.

Abstract: A resistor network having a precise ratio of resistances of all resistors within the network while having a compact layout to minimize area is described. The integrated circuit resistor network has a plurality of unit resistors. Each unit resistor is composed of a thin film resistive material. The area of the thin film resistive material to form the unit resistor is a median value of the resistor elements to be formed into said integrated circuit resistor network. Each unit resistor has a contact means to connect to the plurality of unit resistors. A plurality of metal interconnection segments will connect to the contact means to form said integrated circuit resistor network. A plurality of metal conductive segments are connected to a metal interconnection segments and to external circuitry to connect the external circuitry to the integrated circuit resistor network.

Abstract: At the time of forming an alloy composition gradient layer 4 of gallium arsenide phosphide GaAs.sub.x P.sub.1-x having an arsenic alloy composition x changed in such a range as not to exceed a predetermined alloy composition a with an increase of a layer thickness d between a GaP layer 3 and a composition constant layer 5 of gallium arsenide phosphide GaAs.sub.a P.sub.1-a having the predetermined alloy composition a to be grown above the GaP layer; the alloy composition x is abruptly ascended as in composition ascending zones C11 to C13 with the ascended thickness d of an epitaxial layer and then descended as in crystal stabilizing zones S11 to S13 in such a range as not to cancel the previous ascent amount. One or more combinations of such ascent and descent in the alloy composition are repeated to form as distributed in the alloy composition gradient layer 4, and then the alloy composition x is ascended to the predetermined alloy composition a.

Abstract: A semiconductor package having a board, at least one semiconductor chip, and flat type external connecting terminals, the board having a wiring circuit including connecting portions on a first main surface, the semiconductor being mounted on the first main surface, the flat type external connecting terminals being electrically connected to the semiconductor chip and formed on a second main surface of the board, wherein the flat type external connecting terminals are disposed in such a manner that any straight line which is arbitrarily drawn across the surface of a region to form the flat type external connecting terminals of the board runs on at least one of the flat type external connecting terminals.

Abstract: The present invention provides a base layer structure formed in a hole having an upper portion which has a larger diameter than other portions thereof. The hole is formed in an insulation layer in a semiconductor device. The base layer structure comprises a base layer which extends on at least a part of the upper portion of the hole and over at least a part of the insulation layer in the vicinity of a top of the hole, wherein the base layer extending on the upper portion has an effective thickness in an elevational direction, which is thicker than a thickness of the base layer over the insulation film and also thicker than a critical thickness which allows that at least a part of the base layer on the upper portion of the hole remains after an anisotropic etching process, whilst the base layer having extended over the insulation layer is etched by the anisotropic etching process.

Abstract: A semiconductor device has: a substantially flat surface which is formed on a semiconductor substrate and has a predetermined pattern, in which an insulating layer is embedded; an interlayer insulator film formed on the surface, the interlayer insulator film having a protective layer for protecting the semiconductor substrate; and formed on the interlayer insulator film and adapted for bonding a wire thereto. In addition, a method for manufacturing a semiconductor device comprises the steps of: forming a semiconductor substrate having a surface which has a groove in which an insulating layer is embedded; forming a protective coat for protecting the surface of the semiconductor substrate, on the upper surface of the insulating layer embedded in the groove; and forming an electrode on the protective coat.

Abstract: In an input protection circuit having an SOI structure for protecting a MOSFET against breaking caused by a high voltage such as static electricity, a trench is provided in an SOI substrate to vertically pass through a silicon layer and a buried oxide film and reach the interior of a P-type silicon substrate. An n.sup.+ polysilicon layer is buried in the trench, to be connected with the silicon substrate by a P-N junction. A wire is connected to the n.sup.+ polysilicon layer. An end of the wire is connected to an input pad, and another end thereof is connected to an internal circuit. An input voltage is limited by an avalanche breakdown at the P-N junction in the interface between the n.sup.+ polysilicon layer and the P-type silicon substrate.

Abstract: A semiconductor temperature sensor comprises independent current sources and bipolar transistors connected to form a Darlington circuit. The bipolar transistors have electrodes each connected to one of the current sources. An output voltage of the semiconductor temperature sensor is adjusted by trimming a current value of at least one of the current sources.

Abstract: A high-frequency input/output terminal comprises a lower dielectric substrate in which are formed a bottom face ground layer, side ground layers, a line conductor and cofacial ground layers (formed on both sides of the line conductor on one and the same face of the lower dielectric substrate); and an upper dielectric substrate joined to the lower dielectric substrate so that portions of the line conductor and cofacial ground layers are sandwiched between the lower and upper dielectric substrate. In order to suppress return and insertion losses of signal in millimeter wave range due to a difference in transmission mode to improve transmission characteristics, the upper dielectric substrate is made thicker than the lower dielectric substrate. The width of the portion of the line conductor which is sandwiched between the lower dielectric substrate and the upper dielectric substrate is smaller than that of another portion. The cofacial ground layers are projected toward the line conductor.

Abstract: A semiconductor integrated circuit includes a fuse element located on an insulating layer. The surface of the insulating layer is substantially smooth. The insulating layer is located over a capacitor. Wiring is located on the insulation layer. The fuse element and the wiring include the same material.

Abstract: An n type diffusion region and a p type diffusion region are formed in a region sandwiched between trenches arranged at a first main surface of a semiconductor substrate. A p type well is formed in the n- and p-type diffusion regions nearer the first main surface. A source n.sup.+ diffusion region is formed at the first main surface within the p type well. A gate electrode layer is formed opposite to the p type well sandwiched between the n type diffusion region and the source n.sup.+ diffusion region with a gate insulating layer disposed therebetween. The n- and p-type diffusion regions each have an impurity concentration distribution diffused from a sidewall surface of a trench. Thus, a fine, micron-order pn repeat structure can be achieved with sufficient precision and a high breakdown voltage semiconductor device is thus obtained which has superior on-state voltage and breakdown voltage as well as fast switching characteristics.