Abstract: An integrated circuit fabrication process is provided in which an interconnect having a least one vertical sidewall surface is formed. The interconnect thusly formed allows for higher packing density within the ensuring integrated circuit since the interconnect requires less space to accommodate the same current density as an interconnect having sloped (i.e., non-vertical) sidewall surfaces. A semiconductor topography is provided which includes transistors arranged upon and within a silicon-based substrate. A first interlevel dielectric is deposited across the semiconductor topography, and portions of the dielectric are removed to form vias to select portions of the transistors. Conductive plugs are formed exclusively within the vias. An insulating material patterned with vertical sidewall surfaces is then formed across the first interlevel dielectric and a portion of the plugs. The insulating material is then patterned.

Abstract: A process of fabricating a mask type ROM is described wherein second type impurity ions are implanted into a semiconductor substrate having a first opposite type background impurity to form a depletion region adjacent the surface. A plurality of parallel nitride lines are formed on the surface, and a first gate oxide formed on the spaces between the nitride lines. Subsequently, a first layer of doped polycrystalline silicon is deposited over the nitride lines, and the layer etched back to expose the top surfaces of the nitride lines. After the nitride lines are removed, a thin gate oxide layer is formed on the exposed surface of the substrate, and on the surfaces of the resultant first polycrystalline gate electrode lines. A second layer of doped polycrystalline silicon is deposited over the polycrystalline silicon lines, and it is etched back. The etch back of the first, and also the second polycrystalline silicon layers, produces an elongated central depression in each of the resultant lines.

Abstract: Connection between a PMOS transistor and an NMOS transistor is made through a refractory metal salicide layer in the source and drain regions of these transistors. The salicide is low in resistance, thereby partially substituting for a first Al wiring in intracell wiring. The resulting empty area provides a wiring area and, hence, the freedom of chip layout is enhanced. Besides, in a microcell which constitutes a logic circuit, such as a gate array, lateral wiring grid dots can be utilized as a wiring area.

Abstract: The memory cell has transistors that are arranged three-dimensionally. Vertical MOS transistors are arranged on the sidewalls of semiconductor webs, and a plurality of transistors are arranged one above the other on each sidewall. The transistors that are arranged one above the other on a sidewall are connected in series.

Abstract: A process for heat-treating a single crystal silicon wafer to influence the precipitation behavior of oxygen in the wafer in a subsequent thermal processing step. The wafer has a front surface, a back surface, a central plane between the front and back surfaces, and a sink for crystal lattice vacancies at the front surface. In the process, the wafer is subjected to a heat-treatment to form crystal lattice vacancies, the vacancies being formed in the bulk of the silicon. The wafer is then cooled from the temperature of said heat treatment at a rate which allows some, but not all, of the crystal lattice vacancies to diffuse to the crystal lattice vacancy sink to produce a wafer having a vacancy concentration profile in which the peak density is at or near the central plane with the concentration generally decreasing in the direction of the front surface of the wafer.

Abstract: A semiconductor device comprises: a p-type semiconductor substrate (1); an insulating film (3); a gate electrode (2) formed on the substrate via the insulating film; and an n-type source/drain region (5) formed on both sides of a channel forming region (4) located under the gate electrode (2) formed on the substrate (1). In particular, the thickness (T.sub.OX) of the insulating film (3) is determined to be less than 2.5 nm at conversion rate of silicon oxide film (silicon oxide equivalent thickness); a gate length (L.sub.g) of the gate electrode (2) is determined to be equal to or less than 0.3 .mu.m; and further a voltage applied to the gate electrode (2) and the drain region (6) is determined to be 1.5 V or less. Therefore, in the MOSFET having the tunneling gate oxide film (3), the reliability of the transistor under the hot carrier stress can be improved, and the gate leakage current can be reduced markedly, so that the transistor characteristics can be improved markedly.

Abstract: A gate array cell architecture is provided with routing tracks at variable track pitches, thereby increasing the density of the architecture. Orientation of the devices in the gate cells perpendicularly to the routing tracks in the second metallization layer provides an increased porosity in this layer. The orientation allows an N channel device to be made smaller than a P channel device within a gate cell, to provide balanced devices. The perpendicular orientation also provides more contact points for source or drain. When the mulitple contacts are used to connect the device to a power source, the multiple contacts reduce the effective resistance and increase the reliability of the devices.

Abstract: A boundary of a well 102 of a finger structured MOSFET is positioned between an element region 104 and a gate contact 108. With this geometry, it is feasible to reduce the well and attain a decrease in noises. A well electric potential take-out region 105 is disposed in close proximity to the element region 104 within the well 102, thereby making it possible to reduce an areal size of the well and farther decrease the noises.

Abstract: The present invention teaches fabrication of a high-resistance integrated circuit diffusion resistor that uses standard CMOS process steps. By appropriate masking during ion-implantation of source/drain diffusion regions, diffusion resistors created during NMOS source/drain implant may be counterdoped during PMOS source/drain implants and vice-versa. By appropriate choice of relative concentrations of a resistor dopant and counterdopant, and choice of diffusion depths, junction diodes can be formed which create a pinched resistor by constricting the current flow. The relative dopant concentrations can also be chosen to create regions of light effective doping within the diffusion resistor rather than creating junction diodes.

Abstract: In a field effect semiconductor device, in order to increase the operation speed and to make the device finer by lowering the sheet resistance, and to lower the production cost by reducing the process steps, the diffusion layer 17 is surrounded by SiO.sub.2 films 16 and 34 covering the tungsten polycide layer 35 provided as the gate electrode and by the SiO.sub.2 film 12 in the device isolating region, and the titanium polycide layer 44 is brought into contact with the entire surface of the diffusion layer 17 while being extended on the SiO.sub.2 films 12 an d 16. Accordingly, a large allowance in aligning the contact hole 25 with respect to the titanium polycide layer 44 can be assured to make the contact compensation ion implantation unnecessary.

Abstract: The present invention relates to a bidirectional breakover component including a lightly-doped N-type substrate, an upper P-type region extending over practically the entire upper surface of the component except its circumference, a lower P-type uniform layer on the lower surface side of the component, substantially complementary N-type regions respectively formed in the upper region and in the lower layer, a peripheral P-type well, an overdoped P-type region at the upper surface of the well, and lightly-doped N-type regions between the circumference of the upper region and the well.

Abstract: A plurality of transistor cells (36) formed on a semiconductor substrate (32) are connected to form a radio frequency power transistor device (30), whereby individual conductive paths (38) are formed on one side of the substrate (32) to connect respective common gate terminals (34) of adjacent transistor cells (36) in series. A further conductive path (40) is formed on an opposite side of the substrate connecting respective drain terminals (35) of the transistor cells (36) in parallel. A resistive element (42) is interposed in the conductive path (38) connecting each adjacent pair of gate terminals (34). The conductivity of the respective resistive elements (42) is selected so as to adequately provide a conductive pathway for connecting the respective gate terminal outputs, while being sufficiently resistive such that each gate terminal 34 "sees" an electrical circuit termination.

Abstract: An electronic device includes one or more GaAs integrated circuits having a plurality of mutually independent field-effect transistors formed on a GaAs base-member; and one or more high-dielectric-constant base-members including a passive element on a surface thereof or therein.

Abstract: A metallic, lower mounting plate (21) is arranged in an insulating housing (20), a semiconductor body (23) with at least one logic part (24, 25) and at least one power part (26) with vertical MOS transistors being arranged on said lower mounting plate (21). A number of upper mounting plates (22) corresponding to the number of power parts (26) is introduced in the housing (20), said number of upper mounting plates (22) being electrically conductively secured on the upper sides of the power parts (26) of the semiconductor body (23) and being electrically connected to leads (4-6, 13-15). The lower leads covered by the upper leads are thereby recessed.

Abstract: A method for forming a completely buried contact hole and a semiconductor device having a completely buried contact hole in an interconnection structure is disclosed. The completely buried contact hole includes a first insulating layer of a first thermal conductivity having a contact hole formed therein. A region of material of a second thermal conductivity formed in the first insulating layer adjacent the location of the contact hole. The second thermal conductivity is greater than the first thermal conductivity such that the thermal conductivity of the region of material is greater than the thermal conductivity of the insulating layer. A metal is formed in the hole which completely buries the contact hole.

Abstract: A thin film transistor structure for use in driving liquid crystal display elements has a semiconductor active layer, a control electrode layer underlying the active layer with an insulating layer interposed therebetween and first and second main electrode layers formed on or above the active layer in a spaced relation with each other to define a channel in the active layer in cooperation with the control electrode layer between the main electrode layers. The active layer has a first peripheral edge portion generally perpendicular to the direction of the channel and a second peripheral edge portion generally not perpendicular to the direction of the channel. The first and/or second main electrode layer extends over the first and/or second peripheral edge portion of the active layer such that at least a part of the first peripheral edge portion and/or at least part of the second peripheral edge portion of the active layer has its side face directly covered with the main electrode layer.

Abstract: An arrangement and method for making a gate array architecture locates the well taps at the outer corners of each gate cell. The power buses are also located at the outside of the gate cell as well, enabling sharing of the well taps and the power buses. The location of the well taps at the outside corners of the standard cell reduces the number of transistors in a single repeatable cell from eight transistors to four transistors.

Abstract: An integrated circuit, including a resistor having multiple, series-connected resistor segments formed over multiple tubs of semiconductor material of a first polarity in a semiconductor substrate of the opposite polarity. The resistor is implemented with multiple bootstrapping in the sense that all tubs are coupled to a node of the circuit whose potential changes, in response to a changing input signal, in a direction so as to pull the potential at one end of the resistor in a desired direction. Each resistor segment can be formed over a different one of the tubs, or there are more segments than tubs (e.g., more than one segment formed over one of the tubs or at least one segment having no tub under it). In preferred embodiments, the circuit is a high-speed cascode amplifier (or other amplifier), the resistor is a gain-setting resistor coupled to the top rail, and the tubs are coupled to the amplifier's output.

Abstract: Supporting leads extend from one side portion of a package to another side portion thereof and are arranged on both sides of an island such that both ends of the island are supported. An electrode for a fixing potential of a semiconductor chip is connected to these supporting leads by a bonding wire. One end of these supporting lead is located outside a column of an outer lead portion as the same structure as the outer lead portion. Thus, while a structure for commonly using each of the supporting leads as a lead for a fixing potential is adopted, a thermal distribution of the semiconductor chip can be uniformed and no island is inclined at a resin seal time.

Abstract: On the back side of a base body, three layers of polysilicon layer are formed. These polysilicon layers contain boron. A boron concentration C.sub.B(1), C.sub.B(2) and C.sub.B(3) of the first, second and third polysilicon layers from the base body side have a relationship of C.sub.B(1) .ltoreq.C.sub.B(2) .ltoreq.C.sub.B(3). On the other hand, between the polysilicon layers, silicon oxide layers are formed respectively. Upon fabrication of a semiconductor device, at first, a gettering heat treatment is effected for the substrate under a given condition. Thus, contaminating impurity is captured at the grain boundary of polysilicon layers formed on the back side of the base body. Next, the polysilicon formed at the most back side is removed by etching. By this, contaminated impurity is removed from the semiconductor substrate.