Abstract: An electrode structure for a semiconductor device is formed on the semiconductor device, consisting of silicon formed on a substrate to detect a physical quantity of the substrate and converting it into an electric signal, and transfers the converted electric signal to the outside. The electrode structure for the semiconductor device has a barrier layer consisting of a high-melting metal nitride and formed on a contact area of the semiconductor device and an electrode wiring formed on the barrier layer. The barrier layer has different composition ratios of the high-melting metal nitride in correspondence to each stage in the thickness of the barrier layer, in which the composition ratios are a composition ratio making a powerful bond performance at a bonding border area with the electrode wiring, and a composition ratio in which a metal element of the electrode wiring does not diffuse into the semiconductor in the barrier layer.

Abstract: Connections between implanted regions in a semiconductor substrate, such as the sources or drains of adjacent transistors, are made by buried conductive implants rather than upper level metalizations. The presence or absence of a connection between two implanted regions is camouflaged by implanting a conductive buried layer of the same doping conductivity as the implanted regions when a connection is desired, and a field implant of opposite conductivity to the implanted regions when no connection is desired, and forming steps into the substrate at the boundaries of the buried layer or field implant that mask the steps formed between different conductivity regions during a selective etch by a reverse engineer. The masking steps are preferably formed by field oxide layers that terminate at the boundaries of the buried layers and field implants.

Abstract: A method, and structure resulting therefrom, of forming a metal silicide at a shallow junction in a single crystal substrate without encroaching on the shallow junction by forming a metal layer on the substrate over the junction followed by forming a layer of a silicon material which reacts with the metal faster than the silicon in the single crystal substrate. Titanium is the preferred metal and amorphous silicon is the preferred silicon layer and is of a thickness to react with all of the titanium. The two layers are rapid thermal annealed to form titanium silicide. A second rapid thermal anneal is performed which converts the majority of the C49 phase of the titanium silicide to a less resistive and more conductive C54 phase and causes a silicon epitaxial layer to form between silicon substrate and the titanium silicide.

Abstract: A ferroelectric semiconductor device (10) and a method of manufacturing the ferroelectric semiconductor device (10). The ferroelectric semiconductor device (10) has a layer (15) of ferroelectric material disposed on a semiconductor substrate (11) and a gate structure (27) formed on the semiconductor substrate (11). A source region (23) and a drain region (24) are formed on the semiconductor substrate such that the source region (23) and the drain region (24) are laterally spaced apart from the gate structure (27).

Abstract: A MOS type field effect transistor including a portion of silicon layer (114) forming an active region (114a) placed between a grid oxide layer (120) and a buried oxide layer (112), and laterally delimited by lateral oxide insulation blocks (116). The portion of the silicon layer (114) has concave edges (122, 124) facing the lateral oxide insulation blocks (116). The transistor is applicable to the manufacture of integrated circuits with low electricity consumption.

Abstract: An integrated semiconductor junction antifuse is formed from either adjacent regions of opposite doping types or spaced apart regions of similar doping type within a substrate. In its unblown state, the junction antifuse forms an open circuit that blocks current from flowing while in the blown state, the junction antifuse conducts current. The junction antifuse is blown by applying a breakdown voltage sufficient to overcome a semiconductor junction so that current flows across the reverse-biased semiconductor junction. As current flows across the reverse-biased junction, dopant migration forms a conductive path so that the junction antifuse no longer forms an open circuit.

Abstract: Two n-channel enhancement type switching transistors are fabricated on an active area in such a manner as to share a common drain region, and gate electrodes are encapsulated in insulating wall structures defining a contact hole over the common drain region so as to allow a bit line to be directly held in contact through the contact hole with the common drain region.

Abstract: A new transistor cell is disclosed in this invention which is formed in a semiconductor substrate with a drain region of a first conductivity type formed at a bottom surface of the substrate. The DMOS cell includes a polysilicon layer constituting a gate supported on a top surface of the substrate, the gate surrounding and defining an outer boundary of the transistor cell having a removed polysilicon opening disposed substantially in a central portion of the cell. The DMOS cell further includes a source region of the first conductivity disposed in the substrate near edges of the removed polysilicon opening with a portion extends underneath the gate. The DMOS cell further includes a body region of a second conductivity type disposed in the substrate occupying an entire region under the removed polysilicon opening thus encompassing the source region and having a portion extends underneath the gate.

Abstract: A semiconductor device and a method of making the semiconductor device, the semiconductor device having a base region wherein the base region is surrounded by a slot. The sideways depletion region of the collector-base junction terminates on the slot thus reducing the sideways spreading of the collector-base depletion region.

Abstract: A lateral thin-film Silicon-On-Insulator (SOI) device includes a lateral semiconductor device such as a diode or MOSFET provided in a thin semiconductor film on a thin buried oxide. The lateral semiconductor device structure includes at least two semiconductor regions separated by a lateral drift region. A top oxide insulating layer is provided over the thin semiconductor film and a conductive field plate is provided on the top oxide insulating layer. In order to provide enhanced device performance, a portion of the top oxide layer increases in thickness in a substantially continuous manner, while a portion of the lateral drift region beneath the top oxide layer decreases in thickness in a substantially continuous manner, both over a distance which is at least about a factor of five greater than the maximum thickness of the thin semiconductor film.

Abstract: A polysilicon resistor is added between a source (ground or power) of an EMI core circuitry and a source of the EMI peripheral circuitry. In this way, the electromagnetic interference of an integrated circuit is reduced. The added polysilicon resistor reduces the di/dt of the current passing between the power and the ground of the EMI core circuitry so that the EMI is reduced.

Abstract: An alignment mark formed on a surface of substrate for aligning with a mask through an irradiation of alignment light, which comprises a step formed with a concave portion and a convex portion and a metallic film deposited along the concave portion and the convex portion. A light absorption layer is formed over at least one of the concave portion and the convex portion reflecting the step, the light absorption layer lying over the concave portion having a different thickness from that of the light absorption layer lying over the convex portion when the light absorption layer is formed over both the concave portion and the convex portion, the light absorption layer comprising a material capable of absorbing at least a portion of wavelength region of the alignment light. The light absorption layer is desirably formed in a larger thickness on the convex portion of the step as compared with that on the concave portion.

Abstract: The present invention sets forth a process of making, and a device comprising, a capacitor with a damascene tungsten lower electrode. The capacitor is manufactured by first depositing an insulating nitride layer on a field oxide layer, followed by deposition of a layer of oxide on the nitride layer. A gap is etched into both the nitride and oxide layers, wherein a lower electrode comprising a damascene tungsten stud is deposited following deposition of a Ti/TiN liner for the stud. An oxide layer is next formed over the stud having a conducting tungsten channel with another Ti/TiN liner disposed therethrough and connecting with the stud. Then, a metal layer is deposited and etched to form both a contact for the stud via connection to the channel, and an upper electrode insulated from the contact.

Abstract: A MOS bipolar transistor is provided which includes a silicon carbide npn bipolar transistor formed on a bulk single crystal n-type silicon carbide substrate and having an n-type drift layer and p-type base layer. A silicon carbide nMOSFET is formed adjacent the npn bipolar transistor such that a voltage applied to the gate of the nMOSFET causes the npn bipolar transistor to enter a conductive state. The nMOSFET has a source and a drain formed so as to provide base current to the npn bipolar transistor when the bipolar transistor is in a conductive state. Also provide are means for converting electrons flowing between the source and the drain into holes for injection into the p-type base layer. Unit cells and methods of forming such devices are also provided.

Abstract: An amorphized implant is performed to retard diffusion of ions in the source and drain regions. By retarding the diffusion of ions in these regions, a shallower junction is advantageously created in the silicon regions of the wafer. A slight degradation in leakage current is obtained if the amorphized implant is performed on both the source and the drain sides of a transistor. However, since the source region is a low voltage region with a very shallow junction, MOSFETs in both n-channel and p-channel regions are formed with improved performance and reliability.A method of fabricating an integrated circuit includes forming a gate electrode over a semiconductor substrate, forming a source mask extending over the drain region of the semiconductor substrate, and implanting an implant species into the source region of the semiconductor substrate to form an amorphous implant layer of the semiconductor substrate.

Abstract: A detector with quantum structure comprising a small-gap semiconductor material inserted between two large-gap semiconductor materials, the structure comprising a coupling grating between the wave to be detected and the detector zone constituted by the small-gap material. Under these conditions, the detector zone may have a very small thickness (typically of the order of 1,000 .ANG.) and lead to a detectivity, limited by the dark current, that is high.

Abstract: In a semiconductor memory device, a tantalum silicon nitride film or hafnium silicon nitride film is provided, as a diffusion barrier layer, between a polysilicon plug which electrically connects a source/drain region to a lower platinum electrode of a capacitor, formed on a silicon substrate, and the lower platinum electrode.The tantalum silicon nitride film has a composition of Ta.sub.X Si.sub.1-X N.sub.Y wherein 0.75 .ltoreq.X.ltoreq.0.95 and 1.0 .ltoreq.Y.ltoreq.1.1.The hafnium silicon nitride film has a composition of Hf.sub.X Si.sub.1-X N.sub.Y wherein 0.2<X<1.0 and 0<Y<1.0.

Abstract: A high frequency bipolar transistor (30, 60) having reduced capacitance and inductance is formed over a substrate (61). The substrate (61) is heavily doped to form a low resistance current path. A lightly doped epitaxial layer (62) isolates the substrate (61) from layers which form the transistor. The epitaxial layer (62) is the same conductivity type as the substrate (61). A topside substrate contact (73) couples an emitter of the transistor (60) to the substrate (61). The backside of the substrate (61) is metalized and conductively attached to a leaded flag of a leadframe (51) thereby eliminating wirebond inductance in the emitter of the transistor.

Abstract: The principle portion of a semiconductor device is made from a polycrystalline silicon semiconductor layer which yields an X ray diffraction pattern or an electron beam pattern with the (311) diffraction peak intensity accounting for 15% or more of the total diffraction peak intensity. A semiconductor device improved in performance and reliability can be obtained by reducing the density of states at the boundary between the polycrystalline silicon film and the gate insulating film.

Abstract: A microstrip line device is disclosed of the type which typically includes a strip conductor disposed on the top of a substrate. The device further includes a layer of dielectric material disposed between the strip conductor and the substrate for reducing the dissipation loss in these devices. In order to accomplish this, the dielectric layer has a dielectric constant which is less than the dielectric constant of the substrate.