Patents Examined by David C Spalla
  • Patent number: 10700055
    Abstract: Disclosed examples provide fabrications methods and integrated circuits with back ballasted NPN bipolar transistors which include an n-type emitter in a P doped region, a p-type base with a first side facing the emitter, and an n-type collector laterally spaced from a second side of the base, where the collector includes a first side facing the second side of the base, an opposite second side, a silicided first collector portion and a silicide blocked second collector portion covered with a non-conductive dielectric that extends laterally between the first collector portion and the second side of the collector to provide back side ballasting for lateral breakdown and low current conduction via a deep N doped region while the vertical NPN turns on at a high voltage.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: June 30, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Akram Ali Salman, Guruvayurappan Mathur, Ryo Tsukahara
  • Patent number: 10700172
    Abstract: In an embodiment, a semiconductor device is provided that includes a semiconductor body having a first conductivity type, a first major surface and a second major surface opposite the first major surface, a gate arranged on the first major surface, a body region having a second conductivity type opposite the first conductivity type, the body region extending into the semiconductor body from the first major surface, a source region having the first conductivity type, the source region being arranged in the body region, a buried channel shielding region having the second conductivity type, a contact region having the second conductivity type, and a field plate arranged in a trench extending into the semiconductor body from the first major surface.
    Type: Grant
    Filed: October 18, 2018
    Date of Patent: June 30, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Michael Hutzler, Franz Hirler, Ralf Siemieniec
  • Patent number: 10693019
    Abstract: Various embodiments of the present application are directed towards a trench capacitor with a high capacitance density. In some embodiments, the trench capacitor overlies the substrate and fills a trench defined by the substrate. The trench capacitor comprises a lower capacitor electrode, a capacitor dielectric layer, and an upper capacitor electrode. The capacitor dielectric layer overlies the lower capacitor electrode and lines the trench. The upper capacitor electrode overlies the capacitor dielectric layer and lines the trench over the capacitor dielectric layer. The capacitor dielectric layer comprises a high ? dielectric material. By using a high ? material for the dielectric layer, the trench capacitor may have a high capacitance density suitable for use with high performance mobile devices.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: June 23, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsin-Li Cheng, Jyun-Ying Lin, Jing-Hwang Yang, Ting-Chen Hsu, Felix Ying-Kit Tsui, Yen-Wen Chen
  • Patent number: 10684401
    Abstract: [Object] To make it possible to improve viewing angle characteristics more. [Solution] Provided is a display device including: a plurality of light emitting sections formed on a substrate; and a color filter provided on the light emitting section to correspond to each of the plurality of light emitting sections. The light emitting sections and the color filters are arranged such that, in at least a partial region in a display surface, a relative misalignment between a center of a luminescence surface of the light emitting section and a center of the color filter corresponding to the light emitting section is created in a plane perpendicular to a stacking direction.
    Type: Grant
    Filed: March 7, 2017
    Date of Patent: June 16, 2020
    Assignee: Sony Corporation
    Inventor: Daisuke Ueda
  • Patent number: 10686092
    Abstract: The invention aims for an avalanche photodiode comprising an absorption zone (2), a multiplication zone (3), a first electrode and a second electrode. The photodiode further comprises a waveguide (10) forming a curved closed circuit capable of guiding a luminous flux over several turns of said circuit. The absorption zone extends over a portion at least of said waveguide, and the multiplication zone, the first and second electrodes extend along one part at least of the curved closed circuit. The waveguide is preferably an edge waveguide forming a ring and comprising an absorption zone made of germanium of width less than 200 nm. The photodiode according to the invention has an improved compacity and an improved bandwidth while limiting the multiplication noise.
    Type: Grant
    Filed: August 17, 2018
    Date of Patent: June 16, 2020
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Karim Hassan, Salim Boutami
  • Patent number: 10672887
    Abstract: A vertical transistor includes a first source/drain region and a second source/drain region vertically disposed relative to the first source/drain region and coupled to the first source/drain region by a fin. A gate dielectric is formed on the fin, and a gate conductor is formed on the gate dielectric in a region of the fin. A shaped spacer is configured to cover a lower portion and sides of the second source/drain region to reduce parasitic capacitance between the gate conductor and the second source/drain region.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: June 2, 2020
    Assignee: International Business Machines Corporation
    Inventors: Junli Wang, Kangguo Cheng, Theodorus E. Standaert, Veeraraghavan S. Basker
  • Patent number: 10665608
    Abstract: A semiconductor device according to an embodiment includes a substrate. A transistor includes a source layer and a drain layer that are provided in a surface region of the substrate and contain impurities. A gate dielectric film is provided on the substrate between the source layer and the drain layer. A gate electrode is provided on the gate dielectric film. A first epitaxial layer is provided on the source layer or the drain layer. A second epitaxial layer is provided on the first epitaxial layer and contains both the impurities and carbon. A contact plug is provided on the second epitaxial layer. A memory cell array is provided above the transistor.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: May 26, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tomonari Shioda, Junya Fujita, Takayuki Ito
  • Patent number: 10665782
    Abstract: A method of forming a semiconductor structure. The method comprises forming a protective portion of a liner on at least a portion of stack structures on a substrate. The protective portion comprises a material formulated to adhere to the stack structures. A conformal portion of the liner is formed on the protective portion of the liner or on the protective portion of the liner and exposed materials of the stack structures. At least one of the protective portion and the conformal portion does not comprise aluminum. Additional methods of forming a semiconductor structure are disclosed, as are semiconductor structures including the liners comprising the protective portion and the conformal portion.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: May 26, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Kyle B. Campbell, Irina Vasilyeva, Farrell M. Good, Vishwanath Bhat, Kyuchul Chong
  • Patent number: 10658410
    Abstract: In some embodiments, a method is provided. The method includes forming a plurality of trenches in a semiconductor substrate, where the trenches extend into the semiconductor substrate from a back-side of the semiconductor substrate. An epitaxial layer comprising a dopant is formed on lower surfaces of the trenches, sidewalls of the trenches, and the back-side of the semiconductor substrate, where the dopant has a first doping type. The dopant is driven into the semiconductor substrate to form a first doped region having the first doping type along the epitaxial layer, where the first doped region separates a second doped region having a second doping type opposite the first doping type from the sidewalls of the trenches and from the back-side of the semiconductor substrate. A dielectric layer is formed over the back-side of the semiconductor substrate, where the dielectric layer fill the trenches to form back-side deep trench isolation structures.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: May 19, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Hung Cheng, Shyh-Fann Ting, Yen-Ting Chiang, Yeur-Luen Tu, Min-Ying Tsai
  • Patent number: 10658278
    Abstract: In described examples, a terminal (e.g., a conductive terminal) includes a base material, a plating stack and a solder finish. The base material can be a metal, such as copper. The plating stack is arranged on a surface of the base material, and includes breaks in the plating stack. The breaks in the plating stack extend from a first surface of the plating stack to a second surface of the plating stack adjacent to the surface of the base material. The solder finish is coated over the breaks in the plating stack.
    Type: Grant
    Filed: August 16, 2018
    Date of Patent: May 19, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Sreenivasan K Koduri
  • Patent number: 10658467
    Abstract: A semiconductor device of an embodiment includes a silicon carbide layer having a first plane and a second plane; a first silicon carbide region of a first conductivity type in the silicon carbide layer; a second silicon carbide region of a second conductivity type between the first silicon carbide region and the first plane; a third silicon carbide region of the second conductivity type between the first silicon carbide region and the first plane, the third silicon carbide region extending in a first direction parallel to the first plane; a first electrode provided on a side of the first plane; a second electrode provided on a side of the second plane; and a metal silicide layer provided between the first electrode and the second silicon carbide region, the metal silicide layer having a portion being in contact with the first plane, and a shape of the portion being an octagon.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: May 19, 2020
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Yoichi Hori
  • Patent number: 10658230
    Abstract: A semiconductor device includes a comprise a substrate including a main zone and an extension zone, vertical channels on the main zone, and an electrode structure including gate electrodes stacked on the substrate. The vertical channel structures extend in a first direction perpendicular to a top surface of the substrate. The gate electrodes include line regions and contact regions. The line regions extend from the main zone toward the extension zone along a second direction the second direction that is perpendicular to the first direction. The contact regions are on ends of the line regions and are thicker than the line regions. A spacing distance in the second direction between the contact regions is greater than a spacing distance in the first direction between the line regions.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: May 19, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chung-Il Hyun, Semee Jang, Sung Yun Lee
  • Patent number: 10658580
    Abstract: A method of forming a semiconductor structure. The method comprises forming a protective portion of a liner on at least a portion of stack structures on a substrate. The protective portion comprises a material formulated to adhere to the stack structures. A conformal portion of the liner is formed on the protective portion of the liner or on the protective portion of the liner and exposed materials of the stack structures. At least one of the protective portion and the conformal portion does not comprise aluminum. Additional methods of forming a semiconductor structure are disclosed, as are semiconductor structures including the liners comprising the protective portion and the conformal portion.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: May 19, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Kyle B. Campbell, Irina Vasilyeva, Farrell M. Good, Vishwanath Bhat, Kyuchul Chong
  • Patent number: 10651053
    Abstract: The present disclosure describes a method of forming a metal insulator metal (MIM) decoupling capacitor that can be integrated (or embedded) into a 3D integrated circuit package such as, for example, a chip-on-wafer-on-substrate (CoWoS) chip package or an integrated fan-out (InFO) chip package. For example, the method includes providing a glass carrier with a protective layer over the glass carrier. The method also includes forming a capacitor on the protective layer by: forming a bottom metal layer on a portion of the protective layer; forming one or more first metal contacts and a second metal contact on the bottom metal layer, where the one or more first metal contacts have a width larger than the second metal contact; forming a dielectric layer on the one or more first metal contacts; and forming a top metal layer on the dielectric layer.
    Type: Grant
    Filed: April 26, 2018
    Date of Patent: May 12, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wen-Shiang Liao, Chewn-Pu Jou
  • Patent number: 10651286
    Abstract: A silicon nitride cap on a gate stack is removed by etching with a fluorohydrocarbon-containing plasma subsequent to formation of source/drain regions without causing unacceptable damage to the gate stack or source/drain regions. A fluorohydrocarbon-containing polymer protection layer is selectively deposited on the regions that are not to be etched during the removal of the nitride cap. The ability to remove the silicon nitride material using gas chemistry, causing formation of a volatile etch product and protection layer, enables reduction of the ion energy to the etching threshold.
    Type: Grant
    Filed: June 17, 2019
    Date of Patent: May 12, 2020
    Assignee: International Business Machines Corporation
    Inventors: Ravi K. Dasaka, Sebastian U. Engelmann, Nicholas C. M. Fuller, Masahiro Nakamura, Richard S. Wise
  • Patent number: 10644137
    Abstract: An apparatus including a transistor device including a body including a channel region between a source region and a drain region; and a gate stack on the body in the channel region, wherein at least one of the source region and the drain region of the body include a contact surface between opposing sidewalls and the contact surface includes a profile such that a height dimension of the contact surface is greater at the sidewalls than at a point between the sidewalls. A method including forming a transistor device body on a circuit substrate, the transistor device body dimension defining a channel region between a source region and a drain region; forming a groove in the body in at least one of the source region and the drain region; and forming a gate stack on the body in the channel region.
    Type: Grant
    Filed: July 2, 2016
    Date of Patent: May 5, 2020
    Assignee: Intel Corporation
    Inventors: Willy Rachmady, Matthew V. Metz, Gilbert Dewey, Sean T. Ma, Chandra S. Mohapatra, Sanaz K. Gardner, Jack T. Kavalieros, Anand S. Murthy, Tahir Ghani
  • Patent number: 10615319
    Abstract: A light emitting device includes: a light-emitting element; a resin package including a plurality of leads including first and second leads, a first resin portion, a second resin portion extending around an element mounting region, and a third resin portion, wherein the plurality of leads and the first resin portion define a recess having an inner side-wall surface; a light-reflective member being located between the inner side-wall surface and the second resin portion inside the recess; and an encapsulant located in a region of the recess that is surrounded by the light-reflective member, the encapsulant covering the second resin portion and the light-emitting element. The second resin portion has a depression in a surface thereof. A part of the encapsulant is located inside the depression of the second resin portion.
    Type: Grant
    Filed: October 18, 2018
    Date of Patent: April 7, 2020
    Assignee: NICHIA CORPORATION
    Inventors: Mitsuhiro Isono, Kensuke Maehara
  • Patent number: 10608076
    Abstract: A system and method for fabricating metal insulator metal capacitors while managing semiconductor processing yield and increasing capacitance per area are described. A semiconductor device fabrication process places a polysilicon layer on top of an oxide layer which is on top of a metal layer. The process etches trenches into areas of the polysilicon layer where the repeated trenches determine a frequency of an oscillating wave structure to be formed later. The top and bottom corners of the trenches are rounded. The process deposits a bottom metal, a dielectric, and a top metal on the polysilicon layer both on areas with the trenches and on areas without the trenches. A series of a barrier metal and a second polysilicon layer is deposited on the oscillating structure. The process completes the MIM capacitor with metal nodes contacting each of the top metal and the bottom metal of the oscillating structure.
    Type: Grant
    Filed: March 22, 2017
    Date of Patent: March 31, 2020
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Richard T. Schultz
  • Patent number: 10608406
    Abstract: A light emitting device includes: a base including: a main body, and a frame disposed on an upper surface of the main body; one or more laser elements disposed on the upper surface of the main body inward of the frame; a cover comprising: a support member that is fixed on an upper surface of the frame and has an opening inside the frame, and a light transmissive portion disposed so as to close the opening; and a lens body disposed above the light transmissive portion. The support member includes; a first portion fixed on the upper surface of the frame, a second portion on which the lens body is disposed, the second portion being positioned inward of and lower than the first portion, and a third portion on which the light transmissive portion is disposed, the third portion being disposed inward of and lower than the second portion.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: March 31, 2020
    Assignee: NICHIA CORPORATION
    Inventors: Takuya Hashimoto, Eiichiro Okahisa
  • Patent number: 10593773
    Abstract: A laterally diffused metal oxide silicon (LDMOS) transistor and a method of making the LDMOS transistor are disclosed. The LDMOS transistor includes a drain drift region formed in a substrate and containing a drain contact region. A gate structure overlies a channel region in the substrate and a first shallow-trench isolation (STI) structure is formed between the drain contact region and the channel region. The first STI structure contains a high-k dielectric and a second STI structure contains silicon dioxide.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: March 17, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Umamaheswari Aghoram, Pushpa Mahalingam, Alexei Sadovnikov, Eugene C Davis