Patents Examined by David C Spalla
  • Patent number: 10319745
    Abstract: A display panel comprises a substrate, a gate line, a data line insulated from the gate line, a thin film transistor electrically connected to the gate line and the data line, wherein the thin film transistor comprises a gate electrode group formed on the substrate, a gate insulating film formed on the gate electrode group, an active layer formed on the gate insulating film to at least partially overlap the gate electrode group and a source electrode and a drain electrode formed on the active layer so as to be spaced apart from each other, wherein the gate electrode group includes a first gate electrode formed on the substrate, a second gate electrode formed on the first gate electrode, and an insulating layer between the first gate electrode and the second gate electrode, and wherein the first gate electrode has reflectivity higher than that of the second gate electrode.
    Type: Grant
    Filed: July 30, 2015
    Date of Patent: June 11, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Dae Young Lee, Byung Du Ahn, Jung Gun Nam, Gug Rae Jo
  • Patent number: 10312363
    Abstract: A semiconductor device may include a device region having one or more active trenches, a field termination region having an edge trench. A depth of the edge trench is larger than a depth of the one or more active trenches. A thickness of an insulation layer in the edge trench is larger than a thickness of an insulation layer in the one or more active trenches. In some embodiments, the first depth is from 1.2 to 2.0 times larger than the second depth, and a first width of the edge trench is 1.5 to 4.0 times larger than a second width of the one or more active trenches. In a cross-sectional view, a gate electrode of the edge trench is laterally offset from the source electrode in a depth direction of the edge trench such that the gate electrode and the source electrode do not overlap.
    Type: Grant
    Filed: February 2, 2018
    Date of Patent: June 4, 2019
    Assignee: SANKEN ELECTRIC CO., LTD.
    Inventors: Shunsuke Fukunaga, Taro Kondo
  • Patent number: 10312138
    Abstract: A semiconductor device includes a comprise a substrate including a main zone and an extension zone, vertical channels on the main zone, and an electrode structure including gate electrodes stacked on the substrate. The vertical channel structures extend in a first direction perpendicular to a top surface of the substrate. The gate electrodes include line regions and contact regions. The line regions extend from the main zone toward the extension zone along a second direction the second direction that is perpendicular to the first direction. The contact regions are on ends of the line regions and are thicker than the line regions. A spacing distance in the second direction between the contact regions is greater than a spacing distance in the first direction between the line regions.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: June 4, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chung-Il Hyun, Semee Jang, Sung Yun Lee
  • Patent number: 10304752
    Abstract: An imaging unit comprising an imaging chip and a mounting substrate that has the imaging chip mounted thereon and includes a first metal layer for outputting a signal generated by the imaging chip to the outside. An imaging apparatus comprises an imaging unit that includes an imaging chip and a mounting substrate that has the imaging chip mounted thereon and includes a first metal layer for outputting a signal generated by the imaging chip to the outside.
    Type: Grant
    Filed: August 7, 2014
    Date of Patent: May 28, 2019
    Assignee: NIKON CORPORATION
    Inventors: Hirofumi Arima, Ryoichi Suganuma, Takuya Sato, Satoru Suzuki
  • Patent number: 10297671
    Abstract: A method is presented for forming a nanosheet structure having a uniform threshold voltage (Vt). The method includes forming a conductive barrier surrounding a nanosheet, forming a first work function conducting layer over the conductive barrier layer, and forming a conducting layer adjacent the first work function conducting layer, the conducting layer defining a first region and a second region. The method further includes forming a second work function conducting layer over the second region of the conducting layer to compensate for threshold voltage offset between the first and second regions of the conducting layer.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: May 21, 2019
    Assignee: International Business Machines Corporation
    Inventors: Ruqiang Bao, Hemanth Jagannathan, Paul C. Jamison, ChoongHyun Lee, Vijay Narayanan, Koji Watanabe
  • Patent number: 10297469
    Abstract: A method for producing an electronic component and an electronic component, having barrier layers for the encapsulation of the component. The method involves providing a substrate (1) with at least one functional layer (22), and an electronic component, applying at least one first barrier layer (3) on the functional layer (22) by way of plasmaless atomic layer deposition (PLALD), and applying at least one second barrier layer (4) on the functional layer (22) by way of plasma-enhanced chemical v0apor deposition (PECVD).
    Type: Grant
    Filed: November 13, 2014
    Date of Patent: May 21, 2019
    Assignee: OSRAM OLED GmbH
    Inventors: Christian Schmid, Tilman Schlenker, Heribert Zull, Ralph Paetzold, Markus Klein, Karsten Heuser
  • Patent number: 10297717
    Abstract: A light-emitting device includes: a semiconductor layered structure; a conductive substrate disposed under the semiconductor layered structure; one or more upper electrodes each disposed on a portion of an upper surface of the semiconductor layered structure; a lower electrode disposed on a lower surface of the semiconductor layered structure; one or more metal members each having light reflectivity and disposed on the lower surface of the semiconductor layered structure in a region between (i) a region directly under a respective one of the one or more the upper electrodes and (ii) the region on which the lower electrode is disposed; one or more first insulating members each disposed on the lower surface of the semiconductor layered structure in the region directly under the respective one of the one or more the upper electrodes; and one or more second insulating members on a lower surface of the metal member.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: May 21, 2019
    Assignee: NICHIA CORPORATION
    Inventors: Yuya Yamakami, Daisuke Morita
  • Patent number: 10297583
    Abstract: An embodiment of the present invention describes a method for forming a doped region at a first major surface of a semiconductor substrate where the first doped region being part of a first semiconductor device. The method includes forming an opening from the first major surface into the semiconductor substrate and attaching a semiconductor die to the semiconductor substrate at the opening. The semiconductor die includes a second semiconductor device, which is a different type of semiconductor device than the first semiconductor device. The method further includes forming a chip isolation region on sidewalls of the opening and surrounding the second semiconductor device, and singulating the semiconductor substrate.
    Type: Grant
    Filed: September 5, 2014
    Date of Patent: May 21, 2019
    Assignee: Infineon Technologies AG
    Inventor: Dietrich Bonart
  • Patent number: 10290676
    Abstract: An integrated circuit is provided that comprises a resistor, a first superconducting structure coupled to a first end of the resistor, and a second superconducting structure coupled to a second end of the resistor. A thermally conductive heat sink structure is coupled to the second end of the resistor for moving hot electrons from the resistor prior to the electrons generating phonons.
    Type: Grant
    Filed: August 15, 2017
    Date of Patent: May 14, 2019
    Assignee: NORTHROP GRUMMAN SYSTEMS CORPORATION
    Inventors: Aaron A. Pesetski, Patrick Alan Loney
  • Patent number: 10290661
    Abstract: A method of fabricating a TFT includes a step of forming a gate electrode, a gate insulation layer, an active layer, a source electrode, a drain electrode, a passivation layer and a connection electrode, wherein a pattern including the gate electrode, the source electrode and the drain electrode, the active layer and the gale insulation layer is formed by one patterning process, a pattern including the passivation layer and a via hole through the passivation layer is formed by one patterning process, and a pattern of the connection electrode is formed by one patterning process to electrically connect the source electrode and the drain electrode with the active layer.
    Type: Grant
    Filed: August 15, 2017
    Date of Patent: May 14, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Wei Yang
  • Patent number: 10290583
    Abstract: An object of the present invention is to shorten the switching delay time of a semiconductor device. Transistor units are provided between a source bus line and a drain bus line that are provided apart from each other in a first direction, and a plurality of gate electrodes that extends in the first direction and is provided apart from each other in a second direction orthogonal to the first direction is provided in the transistor units. One ends of the gate electrodes on the source bus line side are coupled by a gate connection line extending in the second direction, and a gate bus line electrically coupled to the gate connection line is provided above the gate connection line. The gate electrodes and the gate connection line are formed using a wiring layer of the first layer, the source bus line and the drain bus line are formed using a wiring layer of the second layer, and the gate bus line is formed using a wiring layer of the third layer.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: May 14, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Yoshinao Miura
  • Patent number: 10290710
    Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a first gradient layer, two source/drain structures, a second gradient layer, and a gate. The first gradient layer is disposed on the substrate. The two source/drain structures are separately disposed on the first gradient layer. The second gradient layer is disposed on the two source/drain structures and the first gradient layer, and a second portion of the second gradient layer directly contacts a first portion of the first gradient layer. The gate is disposed on the second gradient layer, between the two source/drain structures.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: May 14, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kuo-Chih Lai, Ming-Chang Lu, Wei Chen, Hui-Lin Wang, Yi-Ting Liao, Chin-Fu Lin
  • Patent number: 10290830
    Abstract: An organic light emitting diode display device and a method for manufacturing the same are disclosed where permeation of moisture and oxygen may be prevented. The organic light emitting diode display device includes a protective members including an first inorganic film formed on a substrate to completely cover an organic light emitting diode, an organic film formed on the first inorganic film, and a second inorganic film formed on the first inorganic film and the organic film, wherein the organic film includes a first organic pattern corresponding to upper and side parts of the organic light emitting diode, and at least one second organic pattern being spaced from the first organic pattern and surrounding the first organic pattern, and the second organic pattern has an upper surface having the same height as an upper surface of the first organic pattern.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: May 14, 2019
    Assignee: LG Display Co., Ltd.
    Inventors: Yun-Ho Kook, Tae-Joon Song, Yong-Hee Han
  • Patent number: 10290503
    Abstract: A spacer etching process produces ultra-narrow polysilicon and gate oxides for insulated gates used with insulated gate transistors. Narrow channels are formed using dielectric and spacer film deposition techniques. The spacer film is removed from the dielectric wherein narrow channels are formed therein. Insulating gate oxides are grown on portions of the semiconductor substrate exposed at the bottoms of these narrow channels. Then the narrow channels are filled with polysilicon. The dielectric is removed from the face of the semiconductor substrate, leaving only the very narrow gate oxides and the polysilicon. The very narrow gate oxides and the polysilicon are separated into insulated gates for the insulated gate transistors.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: May 14, 2019
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventor: Paul Fest
  • Patent number: 10283674
    Abstract: Described herein are solid-state devices based on graphene in a Field Effect Transistor (FET) structure that emits high frequency Electromagnetic (EM) radiation using one or more DC electric fields and periodic magnetic arrays or periodic nanostructures. A number of devices are described that are capable of generating and emitting electromagnetic radiation.
    Type: Grant
    Filed: September 6, 2017
    Date of Patent: May 7, 2019
    Assignee: P-BRANE, LLC
    Inventor: Jay P. Morreale
  • Patent number: 10276484
    Abstract: A package includes a chip formed in a first area of the package and a molding compound formed in a second area of the package adjacent to the first area. A first polymer layer is formed on the chip and the molding compound, a second polymer layer is formed on the first polymer layer, and a plurality of interconnect structures is formed between the first polymer layer and the second polymer layer. A metal-insulator-metal (MIM) capacitor is formed on the second polymer layer and electrically coupled to at least one of the plurality of interconnect structures. A metal bump is formed over and electrically coupled to at least one of the plurality of interconnect structures.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shuo-Mao Chen, Der-Chyang Yeh, Chiung-Han Yeh
  • Patent number: 10276380
    Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming a dielectric layer over a substrate, forming a hard mask (HM) layer over the dielectric layer, forming a fin trench through the HM layer and the dielectric layer and extending down to the substrate, forming a semiconductor feature in the fin trench and removing the HM layer to expose an upper portion of the semiconductor feature to form fin features.
    Type: Grant
    Filed: October 17, 2014
    Date of Patent: April 30, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsung-Yao Wen, Angus Hsiao
  • Patent number: 10276787
    Abstract: An integrated device includes a substrate having a semiconductor surface layer including functional circuitry, a lower metal stack on the semiconductor surface layer, an interlevel dielectric (ILD) layer on the lower metal stack, a top metal layer providing AMR contact pads and bond pads coupled to the AMR contact pads in the ILD layer. An AMR device is above the lower metal stack lateral to the functional circuitry including a patterned AMR stack including a seed layer, an AMR material layer, and a capping layer, wherein the seed layer is coupled to the AMR contact pads by a coupling structure. A protective overcoat (PO layer) is over the AMR stack. There are openings in the PO layer exposing the bond pads.
    Type: Grant
    Filed: February 11, 2016
    Date of Patent: April 30, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Dok Won Lee, William David French, Ricky Alan Jackson, Fuchao Wang
  • Patent number: 10269634
    Abstract: A method embodiment includes forming a hard mask over a dielectric layer and forming a first metal line and a second metal line extending through the hard mask into the dielectric layer. The method further includes removing the hard mask, wherein removing the hard mask defines an opening between the first metal line and the second metal line. A liner is then formed over the first metal line, the second metal line, and the dielectric layer, wherein the liner covers sidewalls and a bottom surface of the opening.
    Type: Grant
    Filed: November 15, 2013
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Hsu Wu, Chien-Hua Huang, Chung-Ju Lee, Tien-I Bao, Shau-Lin Shue
  • Patent number: 10269924
    Abstract: A silicon nitride cap on a gate stack is removed by etching with a fluorohydrocarbon-containing plasma subsequent to formation of source/drain regions without causing unacceptable damage to the gate stack or source/drain regions. A fluorohydrocarbon-containing polymer protection layer is selectively deposited on the regions that are not to be etched during the removal of the nitride cap. The ability to remove the silicon nitride material using gas chemistry, causing formation of a volatile etch product and protection layer, enables reduction of the ion energy to the etching threshold.
    Type: Grant
    Filed: March 18, 2017
    Date of Patent: April 23, 2019
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, ZEON CORPORATION
    Inventors: Ravi K. Dasaka, Sebastian U. Engelmann, Nicholas C. M. Fuller, Masahiro Nakamura, Richard S. Wise