Abstract: Integrated circuit devices may include a fin-type active region extending on a substrate in a first horizontal direction, a gate line extending on the fin-type active region in a second horizontal direction, a source/drain region on the fin-type active region and adjacent to the gate line, and a source/drain contact pattern connected to the source/drain region. The source/drain contact pattern may include a first portion and a second portion, the first portion having a first height, and the second portion having a second height less than the first height. The source/drain contact pattern may include a metal plug in the first and second portions and a conductive barrier film on sidewalls of the metal plug in the first and second portions. A first top surface of the conductive barrier film in the second portion is lower than a top surface of the metal plug in the second portion.

Abstract: In an embodiment, a device includes: a channel region; a gate dielectric layer on the channel region; a first work function tuning layer on the gate dielectric layer, the first work function tuning layer including a p-type work function metal; a barrier layer on the first work function tuning layer; a second work function tuning layer on the barrier layer, the second work function tuning layer including a n-type work function metal, the n-type work function metal different from the p-type work function metal; and a fill layer on the second work function tuning layer.

Abstract: A semiconductor device includes a gate structure, a source/drain epitaxial structure, a front-side interconnection structure, a backside via, an isolation material, and a sidewall spacer. The source/drain epitaxial structure is on a side of the gate structure. The front-side interconnection structure is on a front-side of the source/drain epitaxial structure. The backside via is connected to a backside of the source/drain epitaxial structure. The isolation material is on a side of the backside via and in contact with the gate structure. The sidewall spacer is sandwiched between the backside via and the isolation material. A height of the isolation material is greater than a height of the sidewall spacer.

Abstract: An integrated circuit device includes a fin-type active area along a first horizontal direction on a substrate, a device isolation layer on opposite sidewalls of the fin-type active area, a gate structure along a second horizontal direction crossing the first horizontal direction, the gate structure being on the fin-type active area and on the device isolation layer, and a source/drain area on the fin-type active area, the source/drain area being adjacent to the gate structure, and including an outer blocking layer, an inner blocking layer, and a main body layer sequentially stacked on the fin-type active area, and each of the outer blocking layer and the main body layer including a Si1-xGex layer, where x?0, and the inner blocking layer including a Si layer.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first stacked nanostructure and a second stacked nanostructure formed over a substrate. The semiconductor device structure includes a first gate structure formed over the first stacked nanostructure, and the first gate structure includes a first portion of a gate dielectric layer and a first portion of a filling layer. The semiconductor device structure includes a second gate structure formed over the second stacked nanostructure, and the second gate structure includes a second portion of the gate dielectric layer and a second portion of the filling layer. The semiconductor device structure includes a first isolation layer between the first gate structure and the second gate structure, and a sidewall of the first portion of the gate dielectric layer extends beyond a sidewall of the filling layer.

Abstract: A light emitting diode (LED) package includes a substrate, at least one micro LED chip, a black material layer, and a transparent material layer. The substrate has a width ranging from 100 micrometers to 1000 micrometers. The at least one micro LED chip is electrically mounted on a top surface of the substrate and has a width ranging from 1 micrometer to 100 micrometers. The black material layer covers the top surface of the substrate to expose the at least one micro LED chip. The transparent material layer covers the at least one micro LED chip and the black material layer.

Abstract: A method includes forming a doped region on a top portion of a substrate, forming a first epitaxial layer over the substrate, forming a recess in the first epitaxial layer, the recess being aligned to the doped region, performing a surface clean treatment in the recess, the surface clean treatment includes: oxidizing surfaces of the recess to form an oxide layer in the recess, and removing the oxide layer from the surfaces of the recess, and forming a second epitaxial layer in the recess.

Abstract: A device includes a substrate, a semiconductor layer, a gate structure, source/drain regions, a bottom isolation layer, and a bottom spacer. The semiconductor layer is above the substrate. The gate structure is above the substrate and surrounds the semiconductor layer. The source/drain regions are on opposite sides of the semiconductor layer. The bottom isolation layer is between the substrate and the semiconductor layer. The bottom spacer is on a sidewall of the bottom isolation layer. The bottom isolation layer has a seam therein, and the seam exposes a sidewall of the bottom spacer.

Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type having a first main surface at one side and a second main surface at another side, a trench gate structure including a gate trench formed in the first main surface of the semiconductor layer, and a gate electrode embedded in the gate trench via a gate insulating layer, a trench source structure including a source trench formed deeper than the gate trench and across an interval from the gate trench in the first main surface of the semiconductor layer, a source electrode embedded in the source trench, and a deep well region of a second conductivity type formed in a region of the semiconductor layer along the source trench, a ratio of a depth of the trench source structure with respect to a depth of the trench gate structure being not less than 1.5 and not more than 4.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate and a semiconductor layer formed over a substrate. The semiconductor device further includes an isolation region covering the semiconductor layer and nanostructures formed over the semiconductor layer. The semiconductor layer further includes a gate stack wrapping around the nanostructures. In addition, the isolation region is interposed between the semiconductor layer and the gate stack.

Abstract: Provided is a semiconductor device including a semiconductor substrate, a plurality of semiconductor nanosheets, a plurality of source/drain (S/D) features and a gate stack. The semiconductor substrate includes a first fin and a second fin. The first fin has a first width less than a second width of the second fin, and a top surface of the first fin is lower than a top surface of the second fin. The plurality of semiconductor nanosheets are disposed on the first fin and the second fin. The plurality of source/drain (S/D) features are located on the first fin and the second fin and abutting the plurality of semiconductor nanosheets. The gate stack wraps each of the plurality of semiconductor nanosheets.

Abstract: A magnetoresistance effect element has an underlayer, a first ferromagnetic metal layer, a second ferromagnetic metal layer, and a tunnel barrier layer that is sandwiched between the first and second ferromagnetic metal layers. The tunnel barrier layer has a spinel structure and includes at least one lattice-matched portion, and at least one lattice-mismatched portion. The underlayer is made of a nitride layer; a layer having a (001)-oriented tetragonal or cubic structure; or a layer having a stacked structure with a combination of a nitride layer having a (001)-oriented NaCl structure and a layer having a (001)-oriented tetragonal or cubic structure.

Abstract: According to various aspects, a method of forming one or more remanent-polarizable capacitive structures, the method including forming one or more capacitive structures, each of the one or more capacitive structures includes: one or more electrodes, one or more precursor structures disposed adjacent to the one or more electrodes, wherein each of the one or more precursor structures has a first dimension in a range from about 1 nm to 100 nm and a second dimension in a range from about 1 nm to about 30 nm; and, subsequently, forming one or more remanent-polarizable structures comprising a crystalline remanent-polarizable material based on a crystallization of a precursor material of the one or more precursor structures.

Abstract: There is provided a method for fabricating a device. On a top surface of a substrate, a first layer of a first deposition material is formed. The first layer of the first deposition material is patterned to create a seed pattern of remaining first deposition material. Homoepitaxy is used to grow a second layer of the first deposition material on the seed pattern.

Abstract: A package includes a chip formed in a first area of the package and a molding compound formed in a second area of the package adjacent to the first area. A first polymer layer is formed on the chip and the molding compound, a second polymer layer is formed on the first polymer layer, and a plurality of interconnect structures is formed between the first polymer layer and the second polymer layer. A metal-insulator-metal (MIM) capacitor is formed on the second polymer layer and electrically coupled to at least one of the plurality of interconnect structures. A metal bump is formed over and electrically coupled to at least one of the plurality of interconnect structures.

Abstract: A semiconductor device includes first and second active patterns, a field insulating film between the first and second active patterns, a first gate structure intersecting the first active pattern and including a first gate electrode and a first gate spacer, a second gate structure intersecting the second active pattern and including a second gate electrode and a second gate spacer, a gate separation structure on the field insulating film between the first and second gate structures, the gate separation structure including a gate separation filling film on a gate separation liner, and a connecting spacer between the gate separation structure and the field insulating film, the connecting spacer protruding from a top surface of the field insulating film, and the gate separation liner contacting the connecting spacer and extending along a top surface and sidewalls of the connecting spacer and along the top surface of the field insulating film.

Abstract: Embodiments of the present disclosure relate to forming a nanosheet multi-channel device with an additional spacing layer and a hard mask layer. The additional spacing layer provides a space for an inner spacer above the topmost channel. The hard mask layer functions as an etch stop during metal gate etch back, providing improve gate height control.

Abstract: An integrated circuit device includes a plurality of metal gates each having a metal electrode and a high-? dielectric and a plurality of polysilicon gates each having a polysilicon electrode and conventional (non high-?) dielectrics. The polysilicon gates may have adaptations for operation as high voltage gates including thick dielectric layers and area greater than one ?m2. Polysilicon gates with these adaptations may be operative with gate voltages of 10V or higher and may be used in embedded memory devices.

Abstract: A semiconductor device includes a substrate including NMOS and PMOS regions; first and second active patterns on the NMOS region; third and fourth active patterns on the PMOS region, the third active pattern being spaced apart from the first active pattern; a first dummy gate structure on the first and third active patterns; a second dummy gate structure on the second and fourth active patterns; a normal gate structure on the third active pattern; a first source/drain pattern on the third active pattern and between the normal gate structure and the first dummy gate structure; and a first element separation structure between the first and second dummy gate structures and separating the third and fourth active patterns, wherein the first dummy gate structure includes a first dummy insulation gate intersecting the third active pattern.

Abstract: There is provided a semiconductor device having enhanced operation performance by utilizing a cut region where a gate cut is implemented. There is provided a semiconductor device comprising a first active pattern, a second active pattern, a third active pattern, and a fourth active pattern, all of which extend in parallel in a first direction, and are arranged along a second direction intersecting the first direction; a first gate electrode extended in the second direction on the first to fourth active patterns a first cut region extended in the first direction between the first active pattern and the second active pattern to cut the first gate electrode and a second cut region extended in the first direction between the third active pattern and the fourth active pattern to cut the first gate electrode, wherein one or more first dimensional features related to the first cut region is different from one or more second dimensional features related to the second cut region.