Patents Examined by David Goodwin
  • Patent number: 10224266
    Abstract: According to example configurations herein, a leadframe includes a first conductive strip, a second conductive strip, and a third conductive strip disposed substantially adjacent and substantially parallel to each other. A semiconductor chip substrate includes a first array of switch circuits disposed adjacent and parallel to a second array of switch circuits. Source nodes in switch circuits of the first array are disposed substantially adjacent and substantially parallel to source nodes in switch circuits of the second array. When the semiconductor chip and the leadframe device are combined to form a circuit package, a connectivity interface between the semiconductor chip and conductive strips in the circuit package couples each of the source nodes in switch circuits of the first array and each of the multiple source nodes in switch circuits of the second array to a common conductive strip in the leadframe device.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: March 5, 2019
    Assignee: Infineon Technologies Americas Corp.
    Inventors: Donald J. Desbiens, Gary D. Polhemus, Robert T. Carroll
  • Patent number: 10204856
    Abstract: A structure having fully aligned via connecting metal lines on different Mx levels. The structure may include a first metal line and a second metal line in a first ILD, a cap covering the first ILD, the second metal line and a portion of the first metal line, a second ILD on the cap, and a via that electrically connects the first metal line to a third metal line, wherein the third metal line is above the first metal line and runs perpendicular to the first metal line, the via is fully aligned to the first metal line and the third metal line, and the via electrically connects the first metal line to the third metal line.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: February 12, 2019
    Assignee: International Business Machines Corporation
    Inventors: Daniel C. Edelstein, Nicholas C. Fuller, Elbert E. Huang, Satyanarayana V. Nitta, David L. Rath
  • Patent number: 10175222
    Abstract: A method of manufacturing a nano membrane structure includes preparing a temporary structure having a substrate in which a through-hole is formed in a central portion, and a nano membrane including silicon nitride (SiN), that covers the through-hole on the substrate, and including a central area formed on the through-hole, and a peripheral area formed on the substrate. The method includes preparing an insulating support member including at least one of silicon and a compound containing silicon, and in which a micropore is formed in a central portion, forming a complex structure by performing a hydrophilic surface processing of a surface of the nano membrane and one surface of the insulating support member and by bonding the temporary structure and the insulating support member so that at least a portion of the central area of the nano membrane and the micropore face, and removing the substrate from the complex structure.
    Type: Grant
    Filed: July 16, 2015
    Date of Patent: January 8, 2019
    Assignee: Seoul National University R&DB Foundation
    Inventors: Ki-Bum Kim, Jae-Seok Yu, Hyung-Jun Kim
  • Patent number: 10177047
    Abstract: After forming an interlevel dielectric (ILD) layer over a semiconductor material portion located on a substrate, a gate trench is formed extending through the ILD layer to expose a channel region of the semiconductor material portion. A gate structure is then formed within the gate trench. Epitaxial semiconductor regions are subsequently formed within source/drain contact openings formed on opposite sides of the gate structure, followed by forming source/drain contact structures on the epitaxial semiconductor regions.
    Type: Grant
    Filed: March 1, 2017
    Date of Patent: January 8, 2019
    Assignee: International Business Machines Corporation
    Inventor: Effendi Leobandung
  • Patent number: 10170470
    Abstract: A switching device may include a semiconductor substrate; gate trenches; bottom insulating layers covering bottom surfaces of the gate trenches; gate insulating layers covering side surfaces of the gate trenches; and gate electrodes arranged in the gate trenches. The gate insulating layers in a center portion may have a first thickness and a first dielectric constant, and one or more of the gate insulating layers in a peripheral portion may have, within at least a part of the peripheral portion, a second thickness thicker than the first thickness and a second dielectric constant greater than the first dielectric constant. The semiconductor substrate may include a first region being in contact with the gate insulating layers, a body region being in contact with the gate insulating layers under the first region, and a second region being in contact with the gate insulating layers under the body region.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: January 1, 2019
    Assignees: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATION
    Inventors: Toru Onishi, Katsuhiro Kutsuki, Yasushi Urakami, Yukihiko Watanabe
  • Patent number: 10170598
    Abstract: An object is to provide a semiconductor device including an oxynitride semiconductor whose carrier density is controlled. By introducing controlled nitrogen into an oxide semiconductor layer, a transistor in which an oxynitride semiconductor having desired carrier density and on characteristics is used for a channel can be manufactured. Further, with the use of the oxynitride semiconductor, even when a low resistance layer or the like is not provided between an oxynitride semiconductor layer and a source electrode and between the oxynitride semiconductor layer and a drain electrode, favorable contact characteristics can be exhibited.
    Type: Grant
    Filed: March 1, 2016
    Date of Patent: January 1, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yuta Endo, Toshinari Sasaki, Kosei Noda
  • Patent number: 10170583
    Abstract: A method of making a semiconductor device includes patterning a fin in a substrate; forming a gate between source/drain regions over the substrate, the gate having a dielectric spacer along a sidewall; removing a portion of the dielectric spacer and filling with a metal oxide to form a spacer having a first spacer portion and a second spacer portion; forming a source/drain contact over at least one of the source/drain regions; recessing the source/drain contact and forming a via contact over the source/drain contact; and forming a gate contact over the gate, the gate contact having a first gate contact portion contacting the gate and a second gate contact portion positioned over the first gate contact portion; wherein the first spacer portion isolates the first gate contact portion from the source/drain contact, and the second spacer portion isolates the second gate contact portion from the source/drain contact.
    Type: Grant
    Filed: August 23, 2016
    Date of Patent: January 1, 2019
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES, INC.
    Inventors: Kangguo Cheng, Ruilong Xie, Tenko Yamashita
  • Patent number: 10168450
    Abstract: A silicon wafer having colored top side is disclosed in the present invention. The silicon wafer includes: a wafer; a first semi-conductor layer, formed on at least a portion of a top side of the wafer, having periodical structures to form a grating pattern, and a second semi-conductor layer, formed on the first semi-conductor layer with a bottom side substantially fully contacted with the periodical structures. The first semi-conductor layer and the second semi-conductor layer form a photonic crystal layer and work to reflect a predetermined wavelength range of incident visible light beams. The present invention provides a silicon wafer which can reflect specified color(s) from the surface facing external light beams. Therefore, dies from cutting the silicon wafer with functions to interact with external environment rather than packaged can have advantages to show some specified logo or trademark.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: January 1, 2019
    Assignee: Sunasic Technologies, Inc.
    Inventors: Chi-Chou Lin, Zheng-Ping He
  • Patent number: 10163705
    Abstract: An interconnect structure for an integrated circuit, such as a three dimensional integrated circuit (3DIC), and a method of forming the same is provided. An example interconnect structure includes a substrate, a through via extending through the substrate, and a liner disposed between the substrate and the through via. The substrate includes a tapered profile portion. The tapered profile portion abuts the liner.
    Type: Grant
    Filed: April 28, 2014
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jiung Wu, Kuan-Liang Lai, Ming-Tsu Chung, Hong-Ye Shih, Ku-Feng Yang, Tsang-Jiuh Wu, Wen-Chih Chiou, Shin-Puu Jeng, Chen-Hua Yu
  • Patent number: 10163655
    Abstract: Apparatuses and methods are disclosed herein for densification of through substrate insulating liners. An example method may include forming a through substrate via through at least a portion of a substrate, forming a first liner layer in the through substrate via, and densifying the first liner layer. The example method may further include forming a second liner layer on the first liner layer, and densifying the second liner layer.
    Type: Grant
    Filed: November 20, 2015
    Date of Patent: December 25, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Jin Lu, Rita J. Klein, Diem Thy N. Tran, Irina V. Vasilyeva, Zhiqiang Xie
  • Patent number: 10164032
    Abstract: A semiconductor device and a method of forming the semiconductor device is disclosed. A sacrificial film is used to pattern a contact to a semiconductor structure, such as a contact to a source/drain region of a transistor. The contact may include a tapered profile along an axis parallel to the gate electrode such that an outermost width of the contact decreases as the contact extends away from the source/drain region.
    Type: Grant
    Filed: December 1, 2016
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tung Ying Lee, Chih Chieh Yeh, Jeng-Ya David Yeh, Yuan-Hung Chiu, Chi-Wen Liu, Yee-Chia Yeo
  • Patent number: 10157920
    Abstract: A multiple-fin device includes a substrate and a plurality of fins formed on the substrate. Source and drain regions are formed in the respective fins. A dielectric layer is formed on the substrate. The dielectric layer has a first thickness adjacent one side of a first fin and having a second thickness, different from the first thickness, adjacent an opposite side of the fin. A continuous gate structure is formed overlying the plurality of fins, the continuous gate structure being adjacent a top surface of each fin and at least one sidewall surface of at least one fin. By adjusting the dielectric layer thickness, channel width of the resulting device can be fine-tuned.
    Type: Grant
    Filed: January 29, 2018
    Date of Patent: December 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Wen Liu, Chao-Hsiung Wang
  • Patent number: 10157903
    Abstract: A semiconductor device that improves the discharge capacity with respect to ESD without increasing the surface area of the semiconductor device includes a first conductive portion including plural portions, each of the plural portions having a first type of conductivity, and each of the plural portions extending in a first direction and being arranged in parallel at a distance from each other in a second direction that intersects the first direction; and a second conductive portion including an island portion provided between the respective plural portions of the first conductive portion and extending in the first direction, the second conductive portion having a second type of conductivity that is different from the first type of conductivity.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: December 18, 2018
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Masahiko Higashi
  • Patent number: 10147818
    Abstract: A method of straining a transistor channel zone is provided, including a) forming a plurality of stress blocks based on a material having an intrinsic stress, around a zone based on a semiconducting material in which a transistor channel will be made and on which a transistor gate will be formed, the stress blocks inducing a stress in the zone; b) forming a gate block on the zone, the gate block being disposed between the stress blocks; and c) at least partially removing the stress blocks without removing the gate block, wherein the gate block has a Young's modulus and a thickness such that the stress blocks are at least partially removed in step c) and the induced stress is at least partially maintained in the zone after the stress blocks are at least partially removed.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: December 4, 2018
    Assignee: Commissariat à L'énergie atomique et aux énergies alternatives
    Inventors: Shay Reboh, Benoit Mathieu
  • Patent number: 10128350
    Abstract: Systems and methods are described herein to include an epitaxial metal layer between a rare earth oxide and a semiconductor layer. Systems and methods are described to grow a layered structure, comprising a substrate, a first rare earth oxide layer epitaxially grown over the substrate, a first metal layer epitaxially grown over the rare earth oxide layer, and a first semiconductor layer epitaxially grown over the first metal layer.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: November 13, 2018
    Assignee: IQE plc
    Inventors: Rodney Pelzel, Andrew Clark, Rytis Dargis, Patrick Chin, Michael Lebby
  • Patent number: 10128412
    Abstract: A light emitting device is disclosed. The light emitting device includes a light emitting structure including a first conductive-type semiconductor layer, an active layer, and a second conductive-type semiconductor layer, a light-transmissive conductive layer disposed on the second conductive-type semiconductor layer and having a plurality of open regions through which the second conductive-type semiconductor layer is exposed, and a second electrode disposed on the light-transmissive conductive layer so as to extend beyond at least one of the open regions, wherein the second electrode contacts the second conductive-type semiconductor layer in the open regions and contacts the light-transmissive conductive layer in regions excluding the open regions.
    Type: Grant
    Filed: April 20, 2016
    Date of Patent: November 13, 2018
    Assignee: LG Innotek Co., Ltd.
    Inventors: Min Gyu Na, Sung Ho Choo, Hyun Seoung Ju, Gi Seok Hong, Ji Hee No
  • Patent number: 10104812
    Abstract: A semiconductor module includes a base plate having an inner region adjacent an edge region, a substrate attached to the inner region of the base plate and a heat sink on which the base plate is mounted so that the base plate is interposed between the substrate and the heat sink and at least part of the inner region of the base plate contacts the heat sink. The module further includes a stress relief mechanism configured to permit the base plate to bend away from the heat sink in the edge region responsive to a thermal load so that at least part of the inner region of the base plate remains in contact with the heat sink.
    Type: Grant
    Filed: September 1, 2011
    Date of Patent: October 16, 2018
    Assignee: Infineon Technologies AG
    Inventors: Reinhold Bayerer, Georg Borghoff
  • Patent number: 10103268
    Abstract: A semiconductor device includes a silicon substrate, a silicon germanium (SiGe) layer including a lower portion extending over the silicon substrate and a fin structure protruding above the lower portion, a first dielectric layer disposed over a side surface of the fin structure and a top surface of the lower portion of the silicon germanium (SiGe) layer, an indium gallium arsenide (InGaAs) layer disposed over a surface of the first dielectric layer, a high k oxide layer disposed over a surface of the InGaAs layer, and a metal layer disposed over a surface of the high k oxide layer. The InGaAs layer includes a source region, a channel region, and a drain region. The metal layer is configured to be a first gate electrode, and the fin structure in the SiGe layer is configured to be a second gate electrode.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: October 16, 2018
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Deyuan Xiao
  • Patent number: 10084060
    Abstract: The present disclosure provide a semiconductor structure, including a substrate having a top surface; a gate over the substrate, the gate including a footing region in proximity to the top surface, the footing region including a footing length laterally measured at a height under 10 nm above the top surface; and a spacer surrounding a sidewall of the gate, including a spacer width laterally measured at a height of from about 10 nm to about 200 nm above the top surface. The footing length is measured, along the top surface, from an end of a widest portion of the footing region to a vertical line extended from an interface between a gate body and the spacer, and the spacer width is substantially equal to or greater than the footing length.
    Type: Grant
    Filed: August 15, 2014
    Date of Patent: September 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Zhe-Hao Zhang, Tung-Wen Cheng, Chang-Yin Chen, Kuo Hui Chang, Che-Cheng Chang, Mu-Tsang Lin
  • Patent number: 10056474
    Abstract: A method of introducing strain in a channel region of a FinFET device includes forming a fin structure on a substrate, the fin structure having a lower portion comprising a sacrificial layer and an upper portion comprising a strained semiconductor layer; and removing a portion of the sacrificial layer corresponding to a channel region of the FinFET device so as to release the upper portion of the fin structure from the substrate in the channel region.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: August 21, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Darsen D. Lu, Alexander Reznicek, Kern Rim