Abstract: A plurality of metal interconnections are formed on a semiconductor substrate. The semiconductor substrate is held on a sample stage in a reactor chamber of a plasma processing apparatus and a material gas containing C5F8, C3F6, or C4F6 as a main component is introduced into the reactor chamber, so that a first fluorine-containing organic film having cavities at positions between the metal interconnections is deposited between the metal interconnections and on the top surfaces of the metal interconnections.

Abstract: The present invention is for a compact superconducting power transmission cable operating at distribution level voltages. The superconducting cable is a conductor with a number of tapes assembled into a subconductor. These conductors are then mounted co-planarly in an elongated dielectric to produce a 3-phase cable. The arrangement increases the magnetic field parallel to the tapes thereby reducing ac losses.

Abstract: An integrated circuit (IC) includes a package-integrated Faraday cage assembly to reduce the level of electromagnetic radiation emanating from the IC during operation. The IC uses a number of appropriately spaced leads on the IC package to form part of a Faraday cage surrounding a semiconductor chip within the IC. In one approach, the selected leads are coupled by a conductive member to a conductive cover plate of the IC package that forms an upper boundary of the Faraday cage. When the IC is installed in an external circuit, some or all of the selected leads are coupled together outside of the IC package (e.g., to an electrical ground) to form the lower boundary of the Faraday cage.

Abstract: An integrated type semiconductor device that is capable of reducing cost or improving the reliability of connecting semiconductor chips together or chips to a circuit board. One embodiment of such an integrated type semiconductor device comprises a first semiconductor device (10) having a semiconductor chip (12) with electrodes (16), a stress-relieving layer (14) prepared on the semiconductor chip (12), a wire (18) formed across the electrodes (16) and the stress-relieving layer (14), and solder balls (19) formed on the wire (18) over the stress-relieving layer (14); and a bare chip (20) as a second semiconductor device to be electrically connected to the first semiconductor device (10).

Abstract: A stackable flex circuit IC package includes a flex circuit comprised of a flexible base with a conductive pattern thereon, and wrapped around at least one end portion of a frame so as to expose the conductive pattern to the edge portion. An IC device is mounted within a central aperture in the frame, and is electrically coupled to the conductive pattern. The IC device is sealed in place within the frame with epoxy. A stack of the IC packages is assembled by disposing a conductive epoxy of anisotropic material between the conductive patterns at the edge portions of adjacent IC packages. Application of pressure in a vertical or Z-axis direction between adjacent IC packages completes electrical connections between the individual conductors of the conductive patterns of adjacent IC packages to interconnect the IC packages of the stack, while at the same time maintaining electrical isolation between adjacent conductors within each of the conductive patterns.

Abstract: A stereolithographically fabricated, substantially hermetic package surrounds at least a portion of a semiconductor die so as to substantially hermetically seal the same. Stereolithographic processes may be used to fabricate at least a portion of the substantially hermetic package from thermoplastic glass, other types of glass, ceramics, or metals. The substantially hermetic package may be used with semiconductor device assemblies or with bare or minimally packaged semiconductor dice, including dice that have yet to be singulated from a wafer. The stereolithographic method may include use of a machine vision system including at least one camera operably associated with a computer controlling a stereolithographic application of material so that the system may recognize the position, orientation, and features of a semiconductor device assembly, semiconductor die, or other substrate on which the substantially hermetic package is to be fabricated.

Abstract: The invention provides a printed-wiring board that is capable of preventing the lift-off phenomenon without changing the related process for fabricating related printed-wiring boards. A printed-wiring board of the present invention has the structure in which land portions are formed on both sides (front side and back side) of a board, a through hole is formed through the board, and an electrically conducting layer is formed on the inside peripheral surface of the through hole by means of plating to connect between the above-mentioned land portions of a wiring pattern, wherein the entire surface of the land part including the opening circumference of the through hole is covered with an insulating layer that covers the other part of the wiring pattern on the component side and on the other hand the land part is not covered with an insulating layer and remains exposed on the soldering side.

Abstract: A circuit board assembly containing two pluralities of busbars or wires arranged in a lattice configuration, there being electrical continuity at each of the intersecting points. Slits are provided on each of the busbars which engage each other to complete the lattice. In the case of wires, they are bonded to each other. The conductive member thus formed may be sandwiched between two insulative films and is placed on an insulative plate which, in turn, is enclosed by an electrical connection box. The configuration provides substantial advantages in economy of production, simplified equipment required, and ease of altering the circuitry.

Abstract: The impedance of a newly manufactured data transmission wire pattern can be measured easily and accurately.

Abstract: A printed circuit board and a manufacturing method thereof can realize a thick film laminated structure of single resin material of low dielectric constant without reinforcement material. The printed circuit board is formed with an insulation layer of composite structure of a first resin material of low dielectric constant and a first general base material having different relative dielectric constants, and the insulation layer is disposed between conductor circuits.

Abstract: The flexible interconnecting substrate (1) has a tape-shaped base substrate (10), a plurality of interconnecting patterns (20) formed on a base substrate (10), and a plurality of reinforcing sections (40) formed on the base substrate 10. The plurality of reinforcing sections (40) is formed along the longitudinal direction of the base substrate (10), and at least part of each of the interconnecting patterns (20) is formed at a position away from each of the reinforcing sections (40) in the widthwise direction of the base substrate (10).

Abstract: After a wiring material layer (14) which is made of WSi2 or the like is formed on an insulation film covering a semiconductor substrate (10), a first antireflection coating film (18) which is made of TiON or TiN and a second antireflection coating film (18) which is made of an organic material are sequentially formed on the wiring material layer (14). Resist patterns (20a to 20c) are formed on the second antireflection coating film (18) by photolithography. The dry etching of the second antireflection coating film (18) is performed using the resist patterns (20a to 20c) as masks, after which the dry etching of the first antireflection coating film (16) is conducted using the resist patterns (20a to 20c) and patterns (18a to 18c) of the second antireflection coating film (18) as masks.

Abstract: A method of fabricating a multi-chip module (MCM) package that can fabricate the substrate and the package simultaneously. The bonding pads of a chip are exposed by forming a patterned dielectric layer, and the bonding pads of the chip are electrically connected to the substrate by utilizing to an electroplating to form a metal layer. The present invention provides a fabircating method that can prevent air bubble produced in the patterned dielectric layer and improve the connection ability between the chip and the substrate.

Abstract: A semiconductor processing system having a holding chamber coupled to a mainframe processing system and at least one loadlock chamber coupled to the holding chamber in which unprocessed wafers are transferred from the loadlock chamber to the holding chamber for subsequent processing by the mainframe system.

Abstract: A semiconductor module of the type having a number of semiconductor chips disposed on a chip carrier has at least a second subset of the semiconductor chips disposed above a first subset and conductive connections between the semiconductor chips disposed one above another. The improvement includes flexible tapes forming conductive connections between the first subset of semiconductor chips and the second subset of semiconductor chips. Two of the flexible tapes originate from the first subset and lead to the second subset. The two flexible tapes respectively extend from a contact-making side of the first subset around respectively mutually opposite side faces of the first subset to the second subset.

Abstract: A method of forming an integrated circuit package with a downward-facing chip cavity. A substrate comprising an insulating core layer and a conductive layer is provided. A through-hole is formed in the substrate and an adhesive tape is attached to the surface of the conductive layer. A silicon chip is attached to the exposed adhesive tape surface at the bottom of the first opening. The chip has an active surface and a back surface. The chip further includes a plurality of bonding pads on the active surface. The back surface of the chip is attached to the adhesive tape. A patterned dielectric layer is formed filling the first opening and covering a portion of the adhesive tape, the active surface, the bonding pad and the insulating core layer. The patterned dielectric layer has a plurality of openings that exposes the bonding pads and some through holes. A metallic layer is formed over the exposed surface of the openings and the upper surface of the patterned dielectric layer by electroplating.

Abstract: A semiconductor processing component includes a quartz body characterized by silicon oxide filled micro cracks. The component is utilized as a processing component in a semiconductor furnace system. The quartz body is prepared by cleaning the component to remove a build up silicon layer and to expose micro cracks in the surface of the component and to etch the micro cracks into trenches. A silicon layer is applied onto the processing component body and at least a portion of the silicon is oxidized to silica to fill the trenches in the surface of the component body.

Abstract: There is provided a semiconductor device having a semiconductor chip in which a first protrusion electrode is formed on the semiconductor substrate; and an intermediate substrate which comprises a base substrate, a first external terminal provided in said base substrate, which is joined to said first protrusion electrode, a second external terminal provided in said base substrate, an electrode section being exposed on both surfaces of said base substrate, and a second protrusion electrode formed at one end face of said second external terminal, a plurality of said intermediate substrates being stacked in layers by joining said second protrusion electrode to the other end face of said second external terminal, thus enabling miniaturizing and lightening electronic equipment and realizing high reliability and high performance.

Abstract: A wiring lay-out is provided, for electrically connecting a decoupling cap on a front surface of a multilayer printed circuit board (e.g., a motherboard), with a surface-mounted electrical component (e.g., a micro-ball grid array packaged semiconductor device, such as a PC core logic chip set) on the front surface of the printed circuit board. The wiring lay-out includes a wiring portion formed from a copper plane on the front surface of the printed circuit board; this wiring portion, providing electrical connection from one of the balls of the ball grid array to the decoupling cap, is provided only on the front surface of the printed circuit board. In order to provide a route for the wiring between the electrical component and decoupling cap, vias through the printed circuit board are positioned in a row with bonding pads. All decoupling caps on the printed circuit board are provided on the front surface of the printed circuit board.

Abstract: An entertainment device has a metal shielding member that covers the CPU and image processing unit and a flexible sheet that is interposed between the CPU and metal shielding member. The metal shielding member contains metal oxide magnetic particles for cutting off electromagnetic radiation generated from the CPU and image processing unit, while the flexible sheet is positioned to radiate heat away from the CPU and image processing unit.