Abstract: A bi-level, multilayered package with an integral window for housing a microelectronic device. The device can be a semiconductor chip, a CCD chip, a CMOS chip, a VCSEL chip, a laser diode, a MEMS device, or a IMEMS device. The multilayered package can be formed of a low-temperature cofired ceramic (LTCC) or high-temperature cofired ceramic (HTCC) multilayer processes with the window being simultaneously joined (e.g. cofired) to the package body during LTCC or HTCC processing. The microelectronic device can be flip-chip bonded and oriented so that the light-sensitive side is optically accessible through the window. A second chip can be bonded to the backside of the first chip, with the second chip being wirebonded to the second level of the bi-level package. The result is a compact, low-profile package, having an integral window that can be hermetically-sealed.

Abstract: A vehicle electric power distribution apparatus is provided which includes a plurality of vertically stacked conductive circuit layers, each layer including an array of contact pads, a layer of electrically insulating plastic material between each of the conductive circuit layers, at least some of the contact pads are electrically connected to selected other contact pads of the same conductive circuit layer via integrally formed conductive traces. In addition to the stacked circuit layers the apparatus includes a plurality of conductive pins providing electrical contact between selected contact pads of different selected conductive circuit layers.

Abstract: A flip chip method of joining a chip and a substrate is described. A thermo-compression bonder is utilized to align the chip and substrate and apply a contact force to hold solder bumps on the substrate against metal bumps on the chip. The chip is rapidly heated from its non-native side by a pulse heater in the head of the bonder until the re-flow flow temperature of the solder bumps is reached. Proximate with reaching the re-flow temperature at the solder bumps, the contact force is released. The solder is held above its re-flow temperature for several seconds to facilitate wetting of the substrate's metal protrusions and joining. Metal caps comprised of a noble metal such as palladium is applied to the surface of the metal bumps to prevent the metal bumps (which generally comprise a highly-conductive and highly-reactive metal such as copper) from oxidizing in the elevated temperatures just prior to and during the re-flow operation.

Abstract: A method and implementing system are described in which a tri-plate chip carrier is effective to significantly reduce electromagnetic signal radiation and provide enhanced noise immunity. The tri-plate structure includes a ground layer, a middle signal conducting layer upon which an integrated circuit is mounted, and a top reference potential layer. The middle layer includes groups of printed circuit conductors extending from the chip to the outer edges of the carrier. The top layer is arranged to have separate electrically isolated conducting areas for VDD and ground reference potential connections. The conducting areas are arranged such that each group of signal conductors in the middle signal layer has a ground potential area above it and a ground potential area below it to provide enhanced signal isolation and reduced electromagnetic radiation.

Abstract: In a multilayer wiring board comprising: an insulating board (for example, a glass board 1); and a wiring layer (for example, wiring patterns 2a, 5a and 8a) superimposed on the insulating board through an insulating film (for example, insulating films 3 and 6), a sum (total film thickness) d (&mgr;m) of the thickness of the insulating films 3 and 6 and the internal stress f (MPa) of the insulating film satisfy the following relational expression (1): d×<700(MPa·&mgr;m)  (1)

Abstract: An arrangement of memory-card accommodating portions in a recording and reproducing apparatus includes a plurality of card slots for respectively accommodating memory cards capable of recording and reproducing an audio or image signal disposed adjacent to each other in a mutually overlapping relation, and eject buttons for ejecting the memory cards disposed in individual correspondence with the card slots. A set of at least two of the card slots are arranged so that the memory cards are disposed in parallel with each other.

Abstract: A method of manufacturing a semiconductor chip that has electrode pads on the chip front surface and disposed inside a conductive outer ring. A film circuit is disposed on the chip front surface side. External connection thermals are formed on the film circuit so as to project there from. First leads electrically connect part of the electrode pads to part of the external connection terminals. A second lead electrically connects a grounding or power supply electrode pad to the outer ring, and a third lead electrically connects a grounding or power supply external connection terminal to the outer ring.

Abstract: A multichip module of the present invention includes a substrate having an upper surface, a hole provided on the upper surface of the substrate and a chip provided in the hole. The upper surface of the chip and the upper surface of the substrate forms an even, or substantially even, surface. A first insulating layer is formed on the upper surface of the chip and the upper surface of the substrate and a first wiring layer is formed on the first dielectric layer. A method for manufacturing a multichip module, which includes a substrate having a cavity provided thereon, and a chip, includes providing the chip in the cavity so that the upper surface of the chip and the upper surface of the substrate becomes even, or substantially even. The method also includes forming a first insulating layer on the upper surface of the chip and the upper surface of the substrate, and forming a first wiring layer on the first insulating layer.

Abstract: A PCB assembly which allows economical and reliable rework. The PCB assembly contains a soldermask and a trace with a portion of the trace exposed by a soldermask relief. When one needs to rework the PCB assembly, one bonds a rework wire, using conventional intermetalic bonding materials, to the portion of the trace exposed by the soldermask relief. There is no need to bond a rework wire to a component. Further, there is no need to scrape off the soldermask and possibly damage the traces and/or vias. The bonds are high reliability bonds, and the labor required to perform such bonds are minimal.

Abstract: A structure and methods for reinforcing a semiconductor device to prevent cracking is provided. The device may take the form of a semiconductor chip or a semiconductor chip package. When a semiconductor chip is provided, an adhesion layer is applied over its top surface, followed by the application of a reinforcing layer over the adhesion layer. When a semiconductor chip package is provided, the package first undergoes a cleaning process, followed by the application of an adhesion layer over its top surface and, lastly, the application of a reinforcing layer over the adhesion layer.

Abstract: A module (10) for use with a smart card (50) is disclosed. The module (10) includes a substrate (14) having a first side (16) and a second side (18). The first and second sides each have deposited thereon a metallic layer (19, 21), with the substrate (14) having a thickness of about 125 microns. A die (22) is mounted adjacent the substrate first side (16), with the die (22) being coupled to the substrate first side (16) by a plurality of wire leads (24). A protective coating (26) covers the die (22), with the module having a total thickness of about 525 microns.

Abstract: A chip carrier structure and method for forming the same having a receptor pad formed therein. The structure comprises a circuitized substrate having a conductive element on the surface, an External Dielectric Layer mounted on the circuitized substrate with an opening positioned above the conductive element to form a microvia. The walls of the microvia are first treated to enhance copper adhesion and then are electroplated to provide a receptor pad. Finally, a solder paste is deposited within the microvia to create a solder deposit or bump.

Abstract: Semiconductor devices and methods of manufacturing such devices are disclosed. In one embodiment of this invention, a semiconductor chip is bonded to a first surface of a substrate. The substrate extends beyond the edge of the chip. Signal input/output pads on the chip are juxtaposed with an opening in the substrate. A molded support is formed on the portion of the first surface of the substrate that extends beyond between the sidewall of the edge of the chip. The support prevents bending of the substrate, and allows solder balls to be formed on the entire area of a second surface of the substrate opposite the first surface of the substrate. A heat dissipating plate is mounted on a surface of the chip opposite the substrate. The heat dissipating plate is attached to the support.

Abstract: The optical semiconductor component has a semiconductor body having a first surface with an active region and a second surface with a passive region. An optically transparent layer adjoins at least the optically active region. Conduction paths extend from the active region through the semiconductor body to contact-making points in the region of the second surface.

Abstract: A substrate structure for an integrated circuit package. The substrate is electrically connected to a circuit board and an integrated circuit. The substrate includes a plurality of metal sheets and glue. The metal sheets are arranged opposite to each other. Each of the metal sheets includes a first surface and a second surface. The glue is used for sealing the plurality of metal sheet to form the substrate. The first surfaces and second surfaces of the metal sheets are exposed to the outside of the glue so as to form a plurality of signal input terminals for electrically connecting to the integrated circuit and a plurality of signal output terminals for electrically connecting to the circuit board. Thus, the signal output terminals of the metal sheets can be electrically connected to the circuit board smoothly. Furthermore, the signal transmission distance between the integrated circuit and the circuit board can be shortened so that better signal transmission effect can be obtained.

Abstract: In a semiconductor device such as a high-frequency power amplifier module, a plurality of amplifying means are formed on a semiconductor chip which is mounted on a main surface of a wiring substrate, and electrodes of the semiconductor chip are electrically connected by wires to electrodes of the wiring substrate. In order to make the high-frequency power amplifier module small in size, a substrate-side bonding electrode electrically connected to a wire set at a fixed reference electric potential is place at a location farther from a side of the semiconductor chip than a substrate-side output electrode electrically connected to an output wire. A substrate-side input electrode electrically connected to an input wire is located at a distance from the side of the semiconductor chip about equal to the distance from the side of the semiconductor chip to the substrate-side output electrode, or at a location farther from the side of the semiconductor chip than the substrate-side bonding electrode is.

Abstract: Printed tape is used to form a leads on chip (LOC) ball grid array (BGA) semiconductor device. Leads for a plurality of devices may be applied simultaneously. Bond wires, glob top encapsulant, and the ball grid arrays for the devices may be formed in single process steps. A low temperature curing adhesive material may be used to reduce the effects of differential thermal expansion between the tape and surface of the wafer. In another embodiment of the invention, anisotropically conductive adhesive material is used to connect bond pads on a wafer to leads printed on a tape.

Abstract: A sealed symmetric multilayered package with integral windows for housing one or more microelectronic devices. The devices can be a semiconductor chip, a CCD chip, a CMOS chip, a VCSEL chip, a laser diode, a MEMS device, or a IMEMS device. The multilayered package can be formed of a low-temperature cofired ceramic (LTCC) or high-temperature cofired ceramic (HTCC) multilayer processes with the windows being simultaneously joined (e.g. cofired) to the package body during LTCC or HTCC processing. The microelectronic devices can be flip-chip bonded and oriented so that the light-sensitive sides are optically accessible through the windows. The result is a compact, low-profile, sealed symmetric package, having integral windows that can be hermetically-sealed.

Abstract: A wired board comprises a plurality of bonding pads for connection to connecting terminals of an electronic part, and a plurality of external connection terminals for connection to connecting terminals of an external circuit board such as a motherboard. Each of the bonding pads has a metallized layer, and further has a Ni—B-plated layer, a Ni—P-plated layer and a Au-plated layer which are formed in this order on the metallized layer. The Au-plated layer has the thickness ranging from 1.2 to 3.5 &mgr;m. Each of the external connection terminals has a metallized layer, and further has a Ni—B-plated layer and a Au-plated layer which are formed in this order on the metallized layer of each of the external connection terminals. The Au-plated layer of each of the external connection terminals has the thickness ranging from 0.01 to 1 &mgr;m. A method of producing the wired board is also provided.

Abstract: A sheet such as a polymeric dielectric has elongated lead regions partially separated from the main region of the sheet by gaps in the sheet, and has conductors extending along the lead regions. The lead regions are connected to contacts on a microelectronic element, and the microelectronic element is moved away from the main region of the sheet, thereby bending the lead regions downwardly to form leads projecting from the main region of the sheet.