Abstract: A chip-on-board electronic device includes an electronic device die affixed to a printed circuit board, and electrically interconnected thereto by wirebonds. The electronic device is protected by coating it with a layer of silicon oxynitride and, optionally, an overlying thin layer of a conformal coating such as parylene. Under some circumstances, a protective layer of an organic material may be used instead of the layer of silicon oxynitride. The chip-on-board electronic device may be protected with an overlying layer of the conformal coating.

Abstract: Flexible leads for making electrical connection in microelectronic components includes two metallic layers. The structural or core layer of the lead is formed having a hardness greater than the hardness of the second layer. The relative hardness between the first and second layers is achieved by controlling the grain size during deposition of the respective layers from an electroless or electroplating bath.

Abstract: An inverter capacitor module includes a plurality of substrates having a plurality of ceramic capacitors provided on the top surfaces thereof, and first and second feeding unit lands having conductive films provided on both surfaces thereof and arranged to feed the plurality of ceramic capacitors, the first and second feeding unit lands on both surfaces thereof being electrically connected to each other, a conductive spacer inserted between the plurality of substrates for establishing one of an electrical connection between the first feeding unit lands of an underlying substrate and its overlying substrate and an electrical connection between the second feeding unit lands of an underlying substrate and its overlying substrate, a fixing member arranged to fix the plurality of substrates laminated via the conductive spacer, and a switching module fixed below the bottom substrate among the plurality of substrates that are laminated.

Abstract: A method for assembling semiconductor devices includes providing a first semiconductor device, applying a volume of adhesive material to at least a surface of the first semiconductor device, and positioning a second semiconductor device over the first semiconductor device and a portion of at least one discrete conductive element protruding thereabove. The adhesive material may be applied to a surface of the first semiconductor device prior to positioning the second semiconductor device thereover, or introduced between the first and second semiconductor devices. Upon curing, the predetermined volume of adhesive material spaces the first and second semiconductor devices a predetermined distance apart from one another. Additional semiconductor devices may also be added to the assembly. The first semiconductor device may be associated with a substrate. Semiconductor device assemblies and packages that are at least partially fabricated in accordance with the method are also disclosed.

Abstract: A thermal conductive substrate includes a first electrical insulator layer, a second electrical insulator layer and a lead frame serving as a circuit pattern. The first electrical insulator layer is formed of a thermal conductive resin composition containing a thermosetting resin and an inorganic filler, and is joined to the lead frame. The second electrical insulator layer is provided on the side of the first electrical insulator layer not in contact with the lead frame, and is formed of a thermal conductive resin composition containing the inorganic filler and a resin composition containing the thermosetting resin. The second electrical insulator layer has a higher thermal conductivity than the first electrical insulator layer. Thus, it is possible to achieve higher heat-radiating characteristics and component packaging reliability without deteriorating formability and adhesive characteristics of the electrical insulator layers.

Abstract: The electrical connections of an integrated circuit chip assembly comprised of an integrated circuit chip attached to a substrate are encapsulated and reinforced with a high viscosity encapsulant material by dispensing the encapsulant material through an opening in the substrate into the space between the integrated circuit chip and the substrate. An integrated circuit chin assembly having a reinforced electrical interconnection which is more resistant to weakening as a result of stress created by differences in coefficient of thermal expansion between the integrated circuit chip and the substrate to which the integrated circuit chip is attached is produced.

Abstract: The present invention discloses a method of manufacturing a dual chip package using tape wiring boards. According to the method, an upper tape wiring board, a lower tape wiring board, and a lead frame are prepared. Each of the tape wiring boards includes a polymeric tape having windows patterned therein, metal patterns formed on the lower surface of the polymeric tape at either sides of said windows. The metal patterns have pad connection portions exposed through the window. Lead connection portions extend outwardly from said polymeric tape. An adhesive layer is formed on the lower surface of the tape. A lower chip is attached to a lower surface of the die pad. The lower chip includes an active surface having a plurality of electrode pads at approximately the center and a rear surface attached to the lower surface of the die pad. An upper chip is attached to an upper surface of the die pad.

Abstract: In one embodiment of the invention, a stacking element includes a printed circuit board (PCB) and a plurality of solder bumps. The PCB has a top side and a bottom side. The top side is attached to first pins of a first device. The plurality of solder bumps are on the bottom side and attached to upper areas of second pins of a second device to provide electrical connections between the first pins and the second pins.

Abstract: Assembly of integrated circuit packages, such as BGA packaged devices, using fluidic self-assembly. Functional components, such as integrated circuits, having a wired side are suspended in a fluid and flowed over a substrate. The substrate has a top first dielectric layer and recessed receptor regions for receiving the functional components. The functional components are deposited in the receptor regions using fluidic self-assembly such that the wired side is facing outward from the receptor region. A conductive layer is then formed on the first dielectric layer to form conductive interconnects to the functional components. A second dielectric layer is then formed on the conductive layer. The second dielectric layer has openings for receiving conductive elements. Conductive elements, such as solder balls, are deposited into the openings in the second dielectric layer and contact the conductive layer.

Abstract: A current crowding reduction technique involving the uniform displacement of vias around a bump is provided. By uniformly arranging vias around the bump on an integrated circuit, current can uniformly flow to and from the bump, effectively leading to reduced current density around the bump. Further, a method for reducing current crowding around a bump using an uniform arrangement of vias around the bump is provided.

Abstract: A method for making 0.25 micron semiconductor chips includes using TEOS as the high density plasma (HDP) inter-layer dielectric (ILD). More specifically, after establishing a predetermined aluminum line pattern on a substrate, TEOS is deposited and simultaneously with the TEOS deposition, excess TEOS is etched away, thereby avoiding hydrogen embrittlement of and subsequent void formation in the aluminum lines that could otherwise occur if silane were used as the HDP ILD.

Abstract: A structure for forming a sidewall image transfer conductor having a contact pad includes forming an insulator to include a recess, depositing a conductor around the insulator, and etching the conductor to form the sidewall image transfer conductor, wherein the conductor remains in the recess and forms the contact pad and the recess is perpendicular to the sidewall image transfer conductor.

Abstract: A split-mold, which is used for manufacturing semiconductor devices by resin-encapsulating a substrate on which a plurality of semiconductor chips are formed, includes a first mold and a second mold. The second mold has a pressing surface that is provided with a mold release sheet. The second mold has a mold-release-sheet mechanism holding a mold release sheet outside the pressing surface of the second mold and applying tension to the mold release sheet.

Abstract: A semiconductor package by which contacts are made to both sides of the dice is manufactured on a wafer scale. The back side of the wafer is attached to a metal plate. The scribe lines separating the dice are saw cut to expose the metal plate but the cuts do not extend through the metal plate. A metal layer, which may include a number of sublayers, is formed on the front side of the dice, the metal covering the exposed portions of the metal plate and extending the side edges of the dice. Separate sections of the metal layer may also cover connection pads on the front side of the dice. A second set of saw cuts are made coincident with the first set of saw cuts, using a blade that is narrower than the blade used to make the first set of saw cuts. As a result, the metal layer remains on the side edges of the dice connecting the back and front sides of the dice (via the metal plate).

Abstract: After a trench 54 is formed in a first conductive foil 60A, the circuit elements are mounted, and the insulating resin is applied on the laminated conductive foil 60 as the support substrate. After being inverted, a second conductive foil 60B is etched on the insulating resin 50 as the support substrate for separation into the conductive paths. Accordingly, it is possible to fabricate the circuit device in which the conductive paths 51 and the circuit elements 52 are supported by the insulating resin 50, without the use of the support substrate. And the interconnects L1 to L3 for the circuit are formed, and can be prevented from slipping because of the curved structure and a visor 58.

Abstract: A LED packaging process is to place LED chips at predetermined positions on the printed circuit board substrate, followed by drilling holes to penetrate the substrate, followed by passing the printed circuit board through the solder furnace to completely fill the through-hole position with solder points, followed by using molds to make the soldering points into a groove reflector, followed by placing LED chips in the groove reflector, followed by wire bonding and using encapsulation resin for packaging to form SMD LED with reflectors. In the present invention, the filling with metal conductor in electrode through holes on the printed circuit board to form the groove reflector can enhance the heat dissipation of LED and the brightness of LED, which has the advantageous effects that traditional SMD LED can not have.

Abstract: A multilayered circuit board is constructed such that holes penetrating through second and third dielectric layers, interposed between a pair of electrodes for constructing a capacitor, are filled with a material having a high dielectric constant respectively in a capacitor-forming area, and a plurality of (for example, four) holes are filled with a material having a high magnetic permeability respectively so as to penetrate through first to fifth dielectric layers in a magnetic flux-passing area of a coil constructed by coil electrodes of first to fifth turns in a coil-forming area.

Abstract: In one embodiment of the invention, an embedded enclosure includes a power plane and first and second ground planes. The power plane has a power surface and a power periphery, and couples power to signals of an integrated circuit operating at a fundamental frequency. The first and second ground planes have first and second ground surfaces and first and second ground peripheries, respectively. The first and second ground planes couple ground to the signals. The first and second ground planes are separated from the power plane by first and second distances, respectively. The first and second ground surfaces are larger than the power surface. The first and second ground peripheries extend at least third and fourth distances from the power periphery, respectively. The third and fourth distances are N and M times larger than the first and second distances, respectively.

Abstract: An electrical structure, and associated method of fabrication, for reducing thermally induced strain in a soldered interface, such as a solder ball or a solder column, between a chip carrier (or chip) and an electronic carrier such as a circuit card. The thermally induced strain may be caused during thermal cycling by a mismatch in coefficient of thermal expansion (CTE), and consequent differential rates in thermal expansion, between the chip carrier (or chip) and the electronic carrier. The thermally induced strain may also exist with a large chip carrier characterized by a large temperature difference during thermal transients between the electronic carrier and localized regions of the chip carrier, even in the absence of a CTE mismatch. The electrical structure of the present invention includes an interposing compliant layer of soft and spongy material between the chip carrier (or chip) and the electronic carrier.

Abstract: An integrated circuit including a fabricated die having a cyanate ester buffer coating material thereon. The cyanate ester buffer coating material includes one or more openings for access to the die. A package device may be connected to the die bond pads through such openings. Further, an integrated circuit device is provided that includes a fabricated wafer including a plurality of integrated circuits fabricated thereon. The fabricated wafer has an upper surface with a cyanate ester buffer coating material cured on the upper surface of the fabricated integrated circuit device. Further, a method of producing an integrated circuit device includes providing a fabricated wafer including a plurality of integrated circuits and applying a cyanate ester coating material on a surface of the fabricated wafer. The application of cyanate ester coating material may include spinning the cyanate ester coating material on the surface of the fabricated wafer to form a buffer coat.