Abstract: A digital data processing system comprises a host information generating device, a mass storage subsystem, and a back-up information storage subsystem. The host information generating device generates information and provides it to the mass storage subsystem for storage. The mass storage subsystem receives the generated information from the host information generating device and transfers the generated information to the storage element for storage, and further transfers the generated information to the back-up information storage subsystem. The back-up information storage subsystem receives and stores the generated information from the mass storage subsystem's control element. The back-up information storage subsystem includes a filter/buffer module, a tape log module and a reconstruction module. The filter/buffer module filters and buffers the information received from the mass storage subsystem and provides the buffered information to the tape log module for storage.

Abstract: A decoded instruction cache which stores both directly executable and microcode instructions for concurrent dispatch to a plurality of issue positions. An instruction address required by a superscalar microprocessor is first presented to the decoded instruction cache. If the address is not present in the decoded instruction cache, the instruction bytes are retrieved either from an instruction cache or main memory. In either case, a group of instruction bytes are conveyed to an early decode unit, which performs partial decoding on the instructions therein. These partially decoded instructions are conveyed to the decoded instruction cache for storage. If the first instruction conveyed from the group of instruction bytes is a directly executable instruction, the partially decoded information corresponding to the first instruction is stored in a cache line selected according to the opcode of the first instruction.

Abstract: To realize interprocessor data transfer with the data receive area not fixed in the real memory and with less overhead for synchronization, the send node sends to the destination node, data, a virtual address of a receive area, an address of a receive control flag, a comparison value, and a comparison method. Network adaptor in the destination node judges whether the transfer condition is fulfilled, based on the comparison value, the comparison method and the semaphore in the receive control flag designated by the receive control flag address. Network adaptor further detects whether the receive area of the virtual address is in the main storage, based on the virtual address and the address translation table. The send data is stored in the receive buffer provided in the area for OS, when the above-mentioned condition is not fulfilled or the receive area is not in the main storage.

Abstract: A storage controller calculates an access frequency of each logical disk; that it selects a first logical disk device of which the access frequency exceeds a first predetermined value, the first logical disk device being allocated to a first physical disk device; selects a second logical disk device which has the access frequency equal to or less than a second predetermined value, the second logical disk device being allocated to a second physical disk device; and reallocates the first and second logical devices to the second and the first physical disk devices, respectively.

Abstract: A method for use in a multiprocessor computer system where data objects larger than the address space of a single task are mapped in main memory and the translation lookaside buffer (TLB) is maintained by user mode software is disclosed. The method uses lazy TLB updating that allows stale data to stay in the TLB until it needs to be purged.

Abstract: The invention provides a method and system for performing XOR operations without consuming substantial computing resources. A specialized processor is coupled to the same bus as a set of disk drives; the specialized processor reviews data transfers to and from the disk drives and performs XOR operations on data transferred to and from the disk drives without requiring separate transfers. The specialized processor maintains an XOR accumulator which is used for XOR operations, which records the result of XOR operations, and which is read out upon command of the processor. The XOR accumulator includes one set of accumulator registers for each RAID stripe, for a selected set of RAID stripes. A memory (such as a contents-addressable memory) associates one set of accumulator registers with each selected RAID stripe.

Abstract: An electrically modifiable multilevel non-volatile memory has autonomous refresh means. The multilevel memory has a real-time clock delivering pulses to periodically activate an operation for refreshing the memory cells of the main matrix. The memory has application to the field of large-capacity memories, for example, several tens of megabits and more.

Abstract: The invention includes a computer system having a processor that executes program instructions in privileged and non-privileged execution modes. A user stack is used when the processor is executing in the non-privileged execution mode. A kernel memory stack is used when the processor is executing in the privileged execution mode. The kernel memory stack can grow and shrink dynamically as it is used by its associated thread, through the use of allocate-on-demand memory. A stack overflow handler is executed from within the kernel to resolve allocate-on-demand faults. The stack handler uses only fixed-size memory stacks.

Abstract: In a distributed shared memory system, clusters of symmetric multi-processors are connected to each other by a network. Each symmetric multi-processor includes a plurality of processors, a memory having addresses, and an input/output interface to interconnect the processors. A software implemented method enables data sharing between the clusters of symmetric multi-processors using variable sized quantities of data called blocks. A set of the addresses of the memories are designated as virtual shared addresses to store shared data, and a portion of the virtual shared addresses are allocated to store a shared data structure as one or more blocks. The size of a particular allocated block can vary for different shared data structures. Each block includes an integer number of lines, and each line includes a predetermined number of bytes of shared data. Directory information of a particular block is stored in the memory of a processor designed as the home of the block.

Abstract: A method of improving memory latency associated with a read-type operation in a multiprocessor computer system is disclosed. After a value (data or instruction) is loaded from system memory into a plurality of caches, one cache is identified as a specific cache which contains an unmodified copy of the value that was most recently read, and that cache is marked as containing the most recently read copy, while the remaining caches are marked as containing shared, unmodified copies of the value. When a requesting processing unit issues a message indicating that it desires to read the value, the specific cache transmits a response indicating that it cache can source the value. The response is transmitted in response to the cache snooping the message from an interconnect which is connected to the requesting processing unit. The response is detected by system logic and forwarded from the system logic to the requesting processing unit.

Abstract: A method and apparatus for performing XOR operations on a hard disk drive are provided, which optimize the buffer bandwidth with minimal logic added to the hard disk controller integrated circuit. This is achieved by first storing data from a first source in the buffer memory in an interleaved fashion (i.e. at memory locations having addresses k, k+2 . . . ,k+2n-2) and then sequentially reading each bit set from the buffer memory, XORing it with a corresponding bit set read from a second source and writing the result at the next consecutive location in the buffer memory (i.e. at memory locations having addresses k+1, k+3 . . . k+2n-1). The method can be implemented on existing hard disk controllers with minimal modifications to the hardware. In addition, an embodiment of the invention allows for decoupling of the XOR operation from disk and host transfers, allowing each of those transfers to occur at their maximum rate and using the remaining buffer bandwidth for the XOR operation.

Abstract: Method and apparatus for refreshing DRAM devices (chips) in a computer system. Each DRAM device incorporates circuitry to carry out a burst of RAS cycles during each refresh period. Three different modes are used to trigger the device into refresh. In one mode, each DRAM device incorporates a refresh timer; only one master DRAM device in the system has its refresh timer enabled. The refresh master device generates a refresh request every time the refresh timer times up. A memory controller, after receiving the request, generates an acknowledge signal when certain system conditions are met. All DRAM devices in the system monitor the refresh request and acknowledge handshake continuously. Upon detection of refresh acknowledge, each DRAM device caries out a sequence of predesignated refresh cycles.

Abstract: A method of reducing memory latency associated with a read-type operation in a multiprocessor computer system is disclosed. When a requesting processing unit issues a message indicating that it desires to read a value from an address of a memory device of the computer system, each cache snoops an interconnect to detect the message, and transmits a response to the message, wherein a shared intervention response is transmitted to indicate that a cache containing an unmodified value corresponding to the address of the memory device can source the value. A priority is associated with each response, and system logic detects each response and its associated priority, and forwards a response with a highest priority to the requesting processing unit. The protocol may include prior-art coherency responses such as an invalid response, a modified intervention response, a shared response, and a retry response. Either the retry response or the shared intervention response may be assigned a highest priority.

Abstract: A high speed pseudo-, 8-, 16-, or greater, ported cache memory, and associated effective address generation scheme. Based upon either two-port building blocks, or twice as many single-port building blocks, which are interleaved, the cache memory is arranged as a functional equivalent to a true 8-, 16-, or greater ported interleaved cache memory.

Abstract: A column address selection circuit 1 is provided, which renders all column address signals (CSi), from a start address to a stop address designated by a column address signal (ADCd+ADCu), to be a selective level when a segment address selection signal (SASj) and a block write signal (BW) are at an active level. A segment address selection circuit 2 is provided, which renders all segment address selection signals (SASj), from the start address to the stop address designated by the column address signal (ADCu) of a superordinate side, to be a selection level to supply it to the column address selection circuit 1, when the block write signal (BW) is at the active level.

Abstract: A computer system is disclosed which provides for execution of real-time code from cache memory. A cache management unit provides the real-time code to the cache memory from system memory upon a initiation of a read operation by a processor. Once in cache memory, the processor executes the real-time code from cache memory instead of system memory. The cache management unit detects read hits to cache each time the processor requests an instruction of code that is stored in the cache memory. Lock bits associated with each line of cache lock the contents of the line preventing the line from being overwritten under normal cache operation in which the least most recently used cached data is replaced by presently accessed data. Alternatively, one of a plurality of cache data ways may be dedicated to storing real-time code. Real-time code stored in the dedicated data way is not replaceable and thus is locked.

Abstract: The clock configuration of a printed circuit board (PCB) processor card is described. A processor card including a processor, its associated processor card system bus, a clock generator, and its associated processor card system clock bus is optimized by providing various clock configurations and distributions. In one configuration, multiple clock signals are coupled to a system clock bus for distributing to a host card having system devices. In another configuration, multiple clock signals having various clock rates are coupled to the processor device on the processor card.

Abstract: A method of saving the context of a plurality of registers in a computer processor, requires determining whether the processor registers have a first size or a second size, and saving the contents of the registers in a buffer using a first set of instructions if the processor registers have the first size (e.g., 64 bits), and using a second set of instructions if the processor registers have the second size (e.g., 32 bits). If the processor registers having the first size, the method may further include the steps of determining whether the processor is operating in a first mode (e.g., 64-bit mode) or a second mode (e.g., 32-bit mode), and then saving the contents of the registers in the buffer using the first set of instructions if the processor is operating in the first mode, but using the second set of instructions if the processor is operating in the second mode.

Abstract: A computer system having a bridge and I.sup.2 C EEPROMs is provided with a host I.sup.2 C controller implemented in the bridge for accelerating the reading of the I.sup.2 C EEPROMs. The host I.sup.2 C controller accelerates the reading of I.sup.2 C EEPROMs by executing current address reads of the I.sup.2 C EEPROM when a requested slave address matches a current slave address stored in a current slave address register, and the requested EEPROM address matches a current EEPROM address stored in a current EEPROM address counter. The host I.sup.2 C controller thus eliminates the use of software to track the read accesses of a plurality of masters to an I.sup.2 C EEPROM and also eliminates the use of bus command protocols to support both random reads and current address reads to an I.sup.2 C EEPROM.

Abstract: A method and device for generating address aliases corresponding to memory locations, for avoiding false load/store collisions during memory disambiguation. The alias generator takes advantage of the fact that the entire address range will most likely not be active in the registers at any one time. The subset of the address range that is active can be represented with a smaller number of bits and, hence, the computation of true dependencies is greatly reduced. The address alias generator includes an array for receiving the memory addresses, comparators having inputs connected to each array entry and having outputs connected to an alias encoder, and a control logic unit for writing the given memory address in one of the entries. The output of a given gate is turned on if a memory address is the same as the contents of one of the entry corresponding to that output, and the control means is activated if the output of all of the gates are turned off.