Abstract: A digital data processing apparatus comprising a memory and a central processing unit. The digital data processing apparatus includes a code conversion section. The code conversion section assigns a virtual code for a duplicate code and converts the virtual code into a real code. The memory may consist of an external memory, and the external memory may include the code conversion section. The apparatus also comprises a code inverse section which converts an instruction to an address which is outputted to a memory through a data transmission path.

Abstract: A data processor capable of supporting a plurality of page sizes without increasing the chip occupation area or the power consumption. This data processor for supporting a virtual memory is constructed of a set associative type cache memory having a plurality of banks having their index addresses shared, in which the virtual page size can be set for each page and which includes a TLB to be shared among the plural virtual pages set in various manners. This TLB is provided with a latch field for latching a pair of the virtual page number and the physical page number. The maximum size of the virtual page to be supported is set to the power of two of the minimum size, and the bank number of the TLB is set to no less than the power of two of the former.

Abstract: In a subscriber information service system including a plurality of terminal equipment, and an information server for presenting personal information of a called subscriber to user at each of the terminal equipment, the information server being connected to the plurality of terminal equipment through a communication network, the information server has a subscriber information table consisting of a plurality of personal records each including a personal identifier assigned to a subscriber, a name of the subscriber, status information of the subscriber, and a name and an equipment address of the communication equipment which can be utilized by a user, and a facility of transmitting content data of the personal record of the specific subscriber registrated in the subscriber information table to each of the terminal equipment.

Abstract: A system and method for increasing utilization of a system bus and frame buffer throughput in a graphic display system. The frame buffer is changed from cache inhibited mode to cached mode in order to take advantage of the burst mode of system bus in which a plurality of values are transferred to the frame buffer following one address. Data coherency is maintained between the cache and the frame buffer by invalidating a cache-line before writing to the cache-line, and by explicitly flushing the cache-line after the cache-line is filled with data.

Abstract: A shared system memory buffers data transfers between a plurality of host computers and a plurality of data storage devices. The system memory includes a cache memory and a number of queues and structures to facilitate performance. Management of a replacement queue within the system memory is based on the elapsed time and usage of the data element. If the elapsed time of a data element to be updated is less than a threshold, the data element will remain in the same location of the replacement queue; if the elapsed time is greater than the threshold, the data element is placed at the tail of the replacement queue. The threshold may be determined by dynamically monitoring the stress of the cache memory. The updating of the replacement queue is also affected by the number of times the data element has been accessed while in the replacement queue. The memory also includes a pending write data structure which is not part of the replacement queue.

Abstract: A mirror set copy from a first storage device to a second storage device is performed in a computer system in which write requests are each associated with a reference label. Write requests and a mirror read request are received at the first storage device, and the write requests also are received at the second storage device. The write requests are processed at the first storage device processes. Data is read from the first storage device in response to the mirror read request. The first storage device then sends the data to the second storage device along with a reference label of a write request received at the first storage device prior to sending the data. Thereafter, the second storage device writes the data. Finally, the second storage device processes write requests until the second storage device encounters a write request having the same reference label as that sent with the data.

Abstract: Methods and associated data structures operable in a RAID subsystem to improve I/O performance. A two level cache data structure and associated methods are implemented with a RAID controller. The lower level cache comprises buffers holding recently utilized blocks of the disk devices. The upper level cache records which blocks are present in the lower level cache for each stripe in the RAID level 5 configuration. The upper level cache serves to reduce the overhead processing required of the RAID controller to determine which blocks are present in the lower level cache. Having more rapid access to this information by lowering the processing overhead enables the present invention to rapidly select between different write techniques to post data and error blocks from low level cache to the disk array. A RMW write technique is used to post data and error checking blocks to disk when insufficient information reside in the lower level cache.

Abstract: A memory chip for storage and retrieval of data transmitted as streams of data at sustained peak data transfer rates. The memory chip includes a memory device and an interface capable of achieving high bandwidth throughput. The memory device decodes, arbitrates between, and executes memory access commands, and generates memory access responses. The interface includes a data path, and a number of memory controllers. The interface receives and transmits input and output data streams, and the memory controllers control the flow of the input and output data streams within the memory chip. A packet buffer is coupled between the data path and the memory device. The packet buffer provides for temporary storage of memory access commands, response information, and forwarding data.

Abstract: A method is described for accessing data in a memory that has a first memory plane and a second memory plane. The method includes the step of sending a first plurality of data from the first memory plane to a data port. A second plurality of data from the second memory plane is pre-fetched only while the first plurality of data is sent from the first memory plane. The pre-fetching is performed a first plurality of clock cycles before the second plurality of data is sent to the data port.

Abstract: Processing machines which perform operational processing, data machines which perform data access and/or man-machine interface machines which perform man-machine interface processing, are in a configuration in which they are connected to a network. A first network manager which is connected to the network manages the connection attributes among said machines and the connection relationships among said machines by mutual sending and receiving of electronic statements. A second network manager manages the connection relationships of said machines in a plurality of local networks which comprise a single large network.

Abstract: Disclosed is a memory control device with partitioned memory control for use on a computer system configured based on a shared main memory architecture. The memory control device comprises a main memory controller connected with two sets of access control buses used respectively for partitioned control of the main memory. The main memory is partitioned into a main system dedicated memory segment and a shared resource memory segment respectively for use by the CPU and the peripheral system. A shared data path circuit is used to control data flow on the buses. When the CPU and the peripheral system both want to gain access to the main memory at the same time, the two sets of buses work independently to respectively connect the CPU to the main system dedicated memory segment and the peripheral system to the shared resource memory segment in the main memory for simultaneous, partitioned access to the main memory.

Abstract: A hardware circuit for verifying the execution of software is disclosed wherein the circuit compares a stored value with another value that is stored at at least one predetermined time in the course of program execution. If the two values correspond in some predetermined fashion then it is verified with a level of certainty that the program executed the program steps at or near the predetermined times.

Abstract: In a method and system for performing a memory access cycle from a first processor to a memory address in a multi-processor system, the memory access cycle is initiated, and, prior to completion of the memory access cycle, a snoop routine is initiated with respect to the memory address. The memory access cycle is continued without awaiting responses from another one of the processors if a second one of the processors provides a signal which indicates that immediate completion of the memory access cycle will not disturb the integrity of data stored in the system.

Abstract: A recoverable disk control system for a computer system that includes a checkpoint operation. When an operating system generates a write request to a disk device, the write request and the associated write data are stored into a nonvolatile memory. The operating system is immediately notified as if the write request were completed. The writing the data to the disk device is postponed until the next checkpoint. At the end of the next checkpoint execution, the write request is scheduled for execution. In that case a fault occurs before the write request is scheduled, the write request is discarded.

Abstract: A data processing system (10) flexibly interfaces with both a variety of memory devices and external peripheral devices. A control register (94) is provided for dynamically controlling a timing relationship for read and write accesses executed by the system. A first set of bits (PA) in the control register provides timing control for an initial amount of time required to read a first data value from an external device. A second set of bits (SA) in the control register provides timing control for each successive amount of time required to read a successive data value from the external device.

Abstract: Noise contained in a reproducing image signal is suppressed by performing a filtering operation on an image signal obtained by decoding data that has been coded with a unit of a block consisting of m.times.n pixels. A filter circuit having a plurality of filter characteristics suppresses noise, and a characteristics selection circuit switches the filter characteristics of the filter circuit by use of a quantizing parameter employed for coding the image signal.

Abstract: Memory requests from multiple processors are re-ordered to maximize DRAM row hits and minimize row misses. Requests are loaded into a request queue and simultaneously decoded to determine the DRAM bank of the request. The last row address of the decoded DRAM bank is compared to the row address of the new request and a row-hit bit is set in the request queue if the row addresses match. The bank's state machine is consulted to determine if RAS is low or high, and a RAS-low bit in the request queue is set if RAS is low and the row still open. A row counter is reset for every new access but is incremented with a slow clock while the row is open but not being accessed. After a predetermined count, the row is considered "stale". A stale-row bit in the request queue is set if the decoded bank has a stale row. A request prioritizer reviews requests in the request queue and processes row-hit requests first, then row misses which are to a stale row.

Abstract: An apparatus and method for retrieving a data file from a disk drive storage which provide for overlapping read operations thereby reducing the latency seen by a requesting host computer. The host computer requests the retrieval of a data file and a channel director places that request in a data cache. If the data file is not in the data cache, a disk director reads and transfers the data file from the disk drive to the data cache. At a certain point in the transfer of the data file into the data cache, the disk director places a start read message in the data cache which is then read by the channel director. Upon receipt of the start read message, the channel director begins to read the data file from the data cache, thus reading data from the data cache as the disk director completes writing the data file to the data cache. The channel director can adaptively modify the starting point for reading the data files depending upon the "success" rate of previous read operations.

Abstract: A rotary storage device includes a plurality of disk units, an upper-level interface circuit, a cache controller, a cache memory, and a control processor. In each disk unit, the storage area of each disk is subdivided into an ordinary user data area and a secondary cache data storage area including a group of consecutive cylinders. Data overflowed from the cache memory is sequentially written in the secondary cache data storage area so as to be later transferred therefrom to areas of the user data area according to addresses inherent thereto when traffic of upper-level input/output processing is relatively low. In the case of when data is sought to be accessed in the cache memory during a data read operation, access operations are performed first to the secondary cache data storage area and then to the user data area.

Abstract: A message delivery system, for use with a communication network and in which a network presence is provided for an entity having attributes, delivers a message from a sender to the network presence. In some cases, information identifying the sender is omitted from the message. The delivery system can append non-repudiable sender information to the message. The sender can provide selected attributes as an address, and the delivery system replaces the selected attributes with an address of the network presence without disclosing the address to the sender. A software agent processes the delivered message in accordance with a processing preference included in the entity attributes.