Abstract: An electromagnetic sliding mechanism and an electronic device are provided. The sliding mechanism includes a fixing base, a sliding piece, and an elastic piece. The fixing base and the sliding piece are respectively provided with an electromagnetic element and the two electromagnetic elements correspond to each other. The sliding piece can slide between a first position and a second position with respect to the fixing base. One end of the elastic piece is pivotally connected to the fixing base, and the other end thereof is pivotally connected to the sliding piece to slide synchronously therewith. Via a repulsive magnetic force generated by electro-magnetizing the two electromagnetic elements, the sliding piece slides automatically from the first position to the second position. When the electromagnetic sliding mechanism is applied to the electronic device, two opposite casings of the electronic device can slide with respect to each other.

Abstract: A frequency synthesizer (100) can selectively set an output band of VCO, and consumes less power. The frequency synthesizer (100) has a frequency converting circuit (110) that has a mixer (111) and a frequency divider (112) connected with each other in parallel. The frequency synthesizer (100) uses the frequency divider (112) upon frequency band selection in VCO (101) and uses the mixer (111) upon transmission.

Abstract: An oscillator circuit generates a constant delay time by use of a current source and a load element to determine a frequency of a clock. The oscillator circuit includes an integrator which integrates the clock, a first comparator which compares an output voltage of the integrator with a reference voltage, and a variable current source which changes a current in accordance with the comparison result of the first comparator. The frequency is corrected in accordance with the current of the variable current source.

Abstract: A multi-phase ultra-wideband signal generator uses differential pulse oscillators. The multi-phase ultra-wideband signal generator using differential pulse oscillators includes N pulse oscillators for generating pulse signals based on a supply of power, and further comprises N inverting amplification units for outputting inverted amplified signals of output signals of the N pulse oscillators when a number of pulse oscillators is at least two, wherein, when the number of pulse oscillators is an even or odd number, the pulse oscillators are arrayed such that they have a connection form in which output terminals OUT(+) and OUT(?) of a relevant pulse oscillator are connected to output terminals OUT(+) and OUT(?) of a next pulse oscillator through a relevant inverting amplification unit, and the connection form is consecutively applied to the pulse oscillators.

Abstract: A digital amplitude modulator. The digital amplitude modulator is configured to modulate the amplitude of an input carrier signal based on input digital data and generate a corresponding output signal. The digital amplitude modulator includes a first variable gain amplifier for receiving the input carrier signal and generating a corresponding first amplified carrier signal, a second variable gain amplifier for receiving the input digital data and generating corresponding digital amplitude control data and a plurality of selectively activatable amplifier stages. Each amplifier stage receives a replica of the first amplified carrier signal and generates a corresponding second amplified carrier signal when activated. The output signal corresponds to a combination of the second amplified carrier signals generated by the activated amplifier stages.

Abstract: Systems and methods are provided for controlling headroom of an amplifier (e.g., in a transmitter). A method comprises obtaining a target output power for a current interval and obtaining a target headroom for a subsequent interval. The method continues by adjusting, during the current interval, the power output capability of the amplifier based on the target headroom and adjusting the input power of an input signal based on the target output power, such that the output power of the amplifier is substantially constant during the current interval as the power output capability of the amplifier is adjusted.

Abstract: A method of calibrating oscillators is disclosed that includes searching, in an array storing an operational characteristic of the oscillator, for an index value that is associated with an output of the oscillator; determining that the output is within a predetermined accuracy as compared to a desired output; and generating the output based the index value. An apparatus for performing the method is also disclosed herein.

Abstract: An electronic circuit includes: a circuit generating first and second balanced differential input signals; a first envelope detection circuit including a first output terminal and first and second input terminals receiving the first and second input signals, respectively, via first and second impedance elements, respectively, and outputs from the first output terminal a first output signal that is the sum of the squares of the first and second input signals; a second envelope detection circuit including a second output terminal and third and fourth input terminals receiving the first and second input signals, respectively, via third and fourth impedance elements, respectively, and outputs from the second output terminal a second output signal that is twice the value obtained by squaring the average of the first and second input signals; and a differential circuit generating a differential signal from the first and second output signals.

Abstract: An element for interacting with electromagnetic radiation is disclosed, including a first self-resonant body, a second self-resonant body, and a directional device interposed between the first self-resonant body and the second self-resonant body. The directional device is adapted to inhibit propagation of electromagnetic radiation from the second self-resonant body to the first self-resonant body.

Abstract: A circuit, such as, but not limited to, a digital phase-locked loop (PLL) or a transport timing loop, uses a fractional-N modulator and a fractional-N clock synthesizer to generate a clock signal, such as a transmit clock signal, from a reference clock signal. One embodiment uses a recovered clock signal derived from serial received data as a positive input to a feedback loop, and uses the transmit clock signal as a negative input to the feedback loop. After digital phase detection and digital filtering, a filtered error signal s is generated and used to control a modified fraction for control of the fractional-N synthesizer. Disclosed techniques advantageously exhibit jitter attenuation and have relatively little jitter accumulation, which are useful characteristics in telecommunication and data communication network clocking applications. Embodiments can be applied to loop timing, clock regeneration, and transport timing applications, and can be used when clock holdover is desirable.

Abstract: Provided are a harmonic rejection mixer and a harmonic rejection mixing method. A plurality of oscillator signals having a ? duty cycle and uniform phase differences may be generated and a differential or quadrature mixer with harmonic rejection may be realized by using the oscillator signals.

Abstract: A demodulator is provided for demodulating an amplitude-modulated input signal defined by a carrier signal having a carrier frequency modulated by a modulating signal, the demodulator including an amplifier stage having a gain and structured to receive the amplitude-modulated input signal, and a gain control stage coupled to the amplifier stage and configured to vary the gain of the amplifier stage according to the carrier frequency of the carrier signal.

Abstract: A system may include a first circuit configured to generate a first clock having a first period of oscillation, and a second circuit configured to generate a second clock having a second period of oscillation, where the difference (?T) between the first period of oscillation and the second period of oscillation remains within a specified limit even during variations in temperature and/or during variations in the supply voltage. The system may further include a control circuit, which may receive the first clock and the second clock, and adjust, according to ?T, a first target parameter corresponding to a first number of cycles of the first clock, when a current cycle count of the second clock reaches a second target parameter corresponding to a second number of cycles of the second clock.

Abstract: An optical transmission apparatus according to the present invention connects a terminal apparatus side in which a transmission line is formed by, for example, SONET/SDH, and a WDM side in which a transmission line is formed by, for example, OTU3. The optical transmission apparatus according to the present invention includes a selector that, when an input signal is interrupted or switched, controls a PLL unit so as to switch and obtain a clock signal of a predetermined frequency oscillated by an OSC, corresponding to a frequency of a clock signal of the input signal before being divided to input into the PLL unit, as a clock signal to generate a PLL reference frequency.

Abstract: A time-to-digital converter (TDC) can have a resolution that is finer than the propagation delay of an inverter. In one example, a fractional-delay element circuit receives a TDC input signal and generates therefrom a second signal that is a time-shifted facsimile of a first signal. The first signal is supplied to a first delay line timestamp circuit (DLTC) and the second signal is supplied to a second DLTC. The first DLTC generates a first timestamp indicative of a time between an edge of a reference input signal to the TDC and an edge of the first signal. The second DLTC generates a second timestamp indicative of a time between the edge of the reference input signal and an edge of the second signal. The first and second timestamps are combined and together constitute a high-resolution overall TDC timestamp that has a finer resolution than either the first or second timestamps.

Abstract: One well known problem associated with voltage controlled oscillators or VCOs is phase noise, and it is desirable to reduce phase noise in order to improve VCO performance. Here, a VCO is provided where gain elements are provided that reduce phase noise. These gain elements are generally comprised of oscillator tanks.

Abstract: An object is to provide a PLL having a wide operating range. Another object is to provide a semiconductor device or a wireless tag which has a wide operating range in a communication distance or temperature by incorporating such a PLL. The semiconductor device or the wireless tag includes a first divider circuit; a second divider circuit; a phase comparator circuit to which an output of the first divider circuit and an output of the second divider circuit are provided; a loop filter to which an output of the phase comparator circuit is supplied and in which a time constant is switched in accordance with an inputted signal; and a voltage controlled oscillator circuit to which an output of the loop filter is supplied and which supplies an output to the second divider circuit.

Abstract: The present relates to a fractional-N frequency synthesizer improving noise characteristics and a method thereof.

Abstract: A phase locked loop circuit is provided comprising a voltage controlled oscillator (VCO), frequency divider, phase frequency detector (PFD), charge pump, waveform generator, loop filter, switching circuit, and lock detector. The VCO generates an oscillation signal. The frequency divider multiplies the frequency of the oscillation signal. The PFD compares the frequency-multiplied oscillation signal and an externally inputted reference signal to generate an error signal. The charge pump generates a signal according to the error signal. The loop filter controls the VCO to modulate the frequency of the oscillation signal and generate a spread spectrum clock based on the signal of the charge pump or waveform generator. The lock detector controls the switching circuit to selectively connect the charge pump to the loop filter during a non-lock state and the waveform generator to the loop filter during a lock state.

Abstract: A method for correcting transmission phasing errors in an plurality of antenna elements is provided. The method includes receiving at least a first signal having a first frequency at the plurality of antenna elements at an angle of arrival (AOA). The method also includes identifying an actual fractional wavelength value (ftrue) for the first signal received with respect to a reference location for at least one of the plurality of antenna elements, obtaining a estimated phase propagation of the first signal at the one of the plurality of antenna elements relative to the reference location based at least on configuration data for plurality of antenna elements, and updating the configuration data associated with the AOA for the one of the plurality of antenna elements based on the estimated phase propagation and ftrue.