Harmonic rejection mixer and harmonic rejection mixing method
Provided are a harmonic rejection mixer and a harmonic rejection mixing method. A plurality of oscillator signals having a ⅓ duty cycle and uniform phase differences may be generated and a differential or quadrature mixer with harmonic rejection may be realized by using the oscillator signals.
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This application claims priority from Korean Patent Application No. 10-2009-0061724, filed on Jul. 7, 2009, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
BACKGROUND OF THE INVENTION1. Field of the Invention
Exemplary embodiments of the present invention relate to a harmonic rejection mixer and a harmonic rejection mixing method, and more particularly, to a mixing method and apparatus for generating a plurality of oscillator signals having ⅓ duty cycles and uniform phase differences and rejecting harmonics by using the oscillator signals.
2. Description of the Related Art
As signals of undesired channels are input to a receiver of a broadband wireless communication system, and more particularly, a wireless broadcasting communication system such as an Advanced Television Systems Committee (ATSC) system, these signals may be combined with harmonics of a local oscillator (LO) of the receiver and added to a desired channel during a frequency mixing process. The added signals may act as noise and may reduce a signal-to-noise ratio (SNR) of the receiver.
Methods of reducing harmonic mixing in a broadband receiver may include a method using a radio frequency (RF) filter and a method using a frequency mixer. The RF filter method may simply reject harmonics by using only one filter but may have to use an external element to obtain a desired level of harmonic rejection in consideration of the performance of a system. Meanwhile, the frequency mixer method may combine multi-phase LO signals with an input signal by using a plurality of parallel frequency mixers and may remove an effect due to harmonic mixing by adjusting gains of combined signals. Although this method may realize an on-chip device, LO signals having uniform phase differences may not be easily formed over a broadband and harmonic rejection may be reduced due to mismatches between parallel circuits. A method of dividing a high frequency LO signal may be used to form uniform phase differences over a broadband. However, this method may have a high structural complexity and may increase power consumption.
Accordingly, a frequency mixer rejecting harmonics, with low power consumption may be required.
SUMMARY OF THE INVENTIONAccording to an aspect of an exemplary embodiment of the present invention, there is provided a frequency mixer with harmonic rejection, the mixer including an oscillator unit generating an oscillator signal having a ⅓ duty cycle; and a mixer unit generating an output signal by mixing an input signal with the oscillator signal.
The oscillator unit may include a first oscillator generating a first oscillator signal having a ⅓ duty cycle; and a second oscillator generating a second oscillator signal having a ⅓ duty cycle and a same frequency as and an opposite phase to the first oscillator signal, and the mixer unit may include a first mixer generating a first mixed signal by mixing the input signal with the first oscillator signal; a second mixer generating a second mixed signal by mixing the input signal with the second oscillator signal; and an output unit generating the output signal by subtracting the second mixed signal from the first mixed signal.
According to another aspect of an exemplary embodiment of the present invention, there is provided a frequency mixing method with harmonic rejection, the method including generating an oscillator signal having a ⅓ duty cycle; and generating an output signal by mixing an input signal with the oscillator signal.
The generating of the oscillator signal may include generating a first oscillator signal having a ⅓ duty cycle; and generating a second oscillator signal having a ⅓ duty cycle and a same frequency as and an opposite phase to the first oscillator signal, and the generating of the output signal may include generating a first mixed signal by mixing the input signal with the first oscillator signal; generating a second mixed signal by mixing the input signal with the second oscillator signal; and generating the output signal by subtracting the second mixed signal from the first mixed signal.
According to another aspect of an exemplary embodiment of the present invention, there is provided a ⅓ duty cycle oscillator apparatus including an oscillator unit generating first through fourth oscillator signals having a ½ duty cycle, a same frequency, and phases of 0°, 90°, 180° and 270° respectively; a first division unit generating a fifth oscillator signal having a ⅓ duty cycle and a ⅓ frequency of the first oscillator signal by dividing the first oscillator signal by three; a second division unit generating a sixth oscillator signal having a ⅓ duty cycle and a ⅓ frequency of the second oscillator signal by dividing the second oscillator signal by three; a third division unit generating a seventh oscillator signal having a ⅓ duty cycle and a ⅓ frequency of the third oscillator signal by dividing the third oscillator signal by three; and a fourth division unit generating an eighth oscillator signal having a ⅓ duty cycle and a ⅓ frequency of the fourth oscillator signal by dividing the fourth oscillator signal by three, wherein the fifth through eighth oscillator signals respectively have phases of 0°, 270°, 180° and 90°.
According to another aspect of an exemplary embodiment of the present invention, there is provided a ⅓ duty cycle oscillator signal generating method including generating first through fourth oscillator signals having a ½ duty cycle, a same frequency, and phases of 0°, 90°, 180° and 270° respectively; generating a fifth oscillator signal having a ⅓ duty cycle and a ⅓ frequency of the first oscillator signal by dividing the first oscillator signal by three; generating a sixth oscillator signal having a ⅓ duty cycle and a ⅓ frequency of the second oscillator signal by dividing the second oscillator signal by three; generating a seventh oscillator signal having a ⅓ duty cycle and a ⅓ frequency of the third oscillator signal by dividing the third oscillator signal by three; and generating an eighth oscillator signal having a ⅓ duty cycle and a ⅓ frequency of the fourth oscillator signal by dividing the fourth oscillator signal by three, wherein the fifth through eighth oscillator signals respectively have phases of 0°, 270°, 180° and 90°.
According to another aspect of an exemplary embodiment of the present invention, there is provided a ⅓ duty cycle oscillator apparatus including an oscillator unit generating first and second oscillator signals having a ½ duty cycle, a same frequency, and opposite phases; a first division unit generating a third oscillator signal having a ⅓ duty cycle and a ⅓ frequency of the first oscillator signal by dividing the first oscillator signal by three; and a second division unit generating a fourth oscillator signal having a ⅓ duty cycle and a ⅓ frequency of the second oscillator signal by dividing the second oscillator signal by three; wherein the third and fourth oscillator signals have opposite phases.
According to another aspect of an exemplary embodiment of the present invention, there is provided a ⅓ duty cycle oscillator signal generating method including generating first and second oscillator signals having a ½ duty cycle, a same frequency, and opposite phases; generating a third oscillator signal having a ⅓ duty cycle and a ⅓ frequency of the first oscillator signal by dividing the first oscillator signal by three; and generating a fourth oscillator signal having a ⅓ duty cycle and a ⅓ frequency of the second oscillator signal by dividing the second oscillator signal by three; wherein the third and fourth oscillator signals have opposite phases.
The above and other features of exemplary embodiments of the present invention will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings in which:
Hereinafter, the present invention will be described in detail by explaining exemplary embodiments of the invention with reference to the attached drawings. In the following description of the exemplary embodiments of the present invention, a detailed description of known functions and configurations incorporated herein may be omitted when not necessary to clarify aspects of the exemplary embodiments of the present invention. When a part “comprises” or “includes” an element, unless otherwise described, the part may further comprise or include other elements. For convenience of explanation, if necessary, an apparatus may be described together with a method.
In the drawings, like reference numerals denote like elements and elements illustrated in a different drawing may be referred to when another drawing is described. The sizes of elements in the drawings may be exaggerated for clarity of explanation.
Referring to
Unlike the square wave 201 having a ½ duty cycle, even-order harmonics exist in the square wave 301 having a ⅓ duty cycle. An exemplary embodiment of a method of additionally rejecting even-order harmonics will now be described with reference to
Referring to
Referring to
Referring to
The oscillator 610a may generate an oscillator signal 601a having a ⅓ duty cycle and a frequency that is the same as a carrier frequency of the input signal 101. The oscillator 610b may generate an oscillator signal 601b having a ⅓ duty cycle, a frequency that is the same as that of an oscillator signal 601a, and a phase that is 180°-shifted from that of an oscillator signal 601a. Exemplary waveforms of the oscillator signals 601a and 601b are illustrated in
The mixer 630a mixes the input signal 101 with the oscillator signal 601a so as to generate the output signal 602a, and the mixer 630b mixes the input signal 101 with the oscillator signal 601b so as to generate the output signal 602b. In this exemplary case, since the oscillator signals 601a and 601b have a ⅓ duty cycle, the influence of every-third-order harmonic components is removed. The output unit 640 subtracts the output signal 602b from the output signal 602a so as to generate the output signal 103 from which the influence of even-order harmonic components is removed. Thus, the ultimate output signal 103 may be a baseband signal from which even-order and every-third-order harmonics, and more particularly, second-order through fourth-order harmonics are rejected.
The exemplary harmonic rejection mixer as illustrated in
Referring to
While the switch 740a is open, the current signal IRF 701a flows into a common mode voltage Vcm by a switch 750a controlled by an inverted oscillator signal fs1_b. This structure bypasses the current signal IRF 701a to another region in order to prevent the current signal IRF 701a from being stored in a parasitic capacitor of the switch 750a and thus may influencing the output voltage.
A lower circuit represented by “b” (710b, 730b, 740b, 750b, 701b, 601b and 602b) may operate similarly to the upper circuit, a 180° phase-shifted oscillator signal fs3 601b is used instead of the oscillator signal fs1 601a to remove even-order harmonics and an inverted current signal IRF
The other circuits represented by “c” and “d” (730c, 730d, 740c, 740d, 750c and 750d) may be used to perform a differential operation. The differential circuit is well-known to one of ordinary skill in the art and thus a detailed description thereof is not provided so as not to obscure the subject matter of aspects of exemplary embodiments of the present invention. According to another exemplary embodiment of the present invention, these circuits may be removed and the harmonic rejection mixer may be realized as a single-ended circuit.
Referring to
Referring to
Aspects of the exemplary harmonic rejection mixer illustrated in
Referring to
Referring to circuits 1110a through 1110d of
In order to align the phases of oscillator signals fs1 through fs4, a signal of a particular node may be chosen as an output signal for each phase and a reset signal Reset_b of the flip-flops may be used. In the exemplary embodiment shown in
Referring to
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Referring to
Referring to
Referring to
When a differential mixer is realized, quadrature oscillator signals may not be necessary. Thus, in
Referring to
Referring to
Referring to
Referring to
As described above, a harmonic rejection mixer according to aspects of exemplary embodiments of the present invention may reject harmonics differently than a conventional harmonic rejection mixer using a multi-phase. Unlike a conventional harmonic rejection mixer, which should set a different gain for each phase, a harmonic rejection mixer according to aspects of exemplary embodiments of the present invention may have the same gain and thus may prevent mismatches between parallel circuits. Furthermore, in a harmonic rejection mixer according to aspects of exemplary embodiments of the present invention, since quadrature oscillator signals that may be used in a general receiver are used, an additional multi-phase oscillator signal that may be generated in a conventional harmonic rejection mixer may not need to be generated. Also, since quadrature oscillator signals may be divided by only three, in comparison to a conventional harmonic rejection mixer that may divide higher frequency oscillator signals by a greater number, low power consumption may be achieved.
While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, the exemplary embodiments should be considered in a descriptive sense only and not for purposes of limitation. The terms used herein to describe concepts of exemplary aspects of the present invention are for descriptive purposes only and are not intended to limit the scope of the invention. Accordingly, it will be understood by one of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the following claims.
The scope of the invention is defined not by the detailed description of the invention but by the following claims, and all structural and functional equivalents within the scope will be construed as being included in the present invention. The equivalents should be construed to include equivalents to be developed in the future as well as currently known equivalents, that is, all components invented to perform the same function regardless of their structures. Additionally, expressions such as “at least one of”, when preceding a list of elements, modify the entire list of elements and do not modify each element of the list.
Claims
1. A frequency mixer with harmonic rejection, the mixer comprising:
- an oscillator unit which generates an oscillator signal having a ⅓ duty cycle; and
- a mixer unit which generates an output signal by mixing an input signal with the oscillator signal.
2. The frequency mixer of claim 1, wherein the mixer unit generates the output signal by switching the input signal according to the oscillator signal.
3. The frequency mixer of claim 1, wherein the input signal is a voltage signal,
- wherein the mixer unit comprises:
- a transconductance which converts the input signal into a current signal; and
- a switch which generates the output signal using the current signal, and
- wherein the switch is turned on if the oscillator signal is in an active state, and the switch is turned off if the oscillator signal is in an inactive state.
4. The frequency mixer of claim 1, wherein the oscillator unit comprises:
- a first oscillator which generates a first oscillator signal having a ⅓ duty cycle; and
- a second oscillator which generates a second oscillator signal having a ⅓ duty cycle and a same frequency as and an opposite phase to the first oscillator signal, and
- wherein the mixer unit comprises:
- a first mixer which generates a first mixed signal by mixing the input signal with the first oscillator signal;
- a second mixer which generates a second mixed signal by mixing the input signal with the second oscillator signal; and
- an output unit which generates the output signal by subtracting the second mixed signal from the first mixed signal.
5. The frequency mixer of claim 4, wherein the first mixer generates the first mixed signal by switching the input signal according to the first oscillator signal, and
- wherein the second mixer generates the second mixed signal by switching the input signal according to the second oscillator signal.
6. The frequency mixer of claim 4, wherein the input signal is a voltage signal,
- wherein the first mixer comprises:
- a first transconductance which converts the input signal into a first current signal; and
- a first switch which generates the first mixed signal using the first current signal,
- wherein the first switch is turned on if the first oscillator signal is in an active state, and the first switch is turned off if the first oscillator signal is in an inactive state, and
- wherein the second mixer comprises:
- a second transconductance which converts the input signal into a second current signal; and
- a second switch which generates the second mixed signal using the second current signal,
- wherein the second switch is turned on if the second oscillator signal is in an active state, and the second switch is turned off if the second oscillator signal is in an inactive state.
7. A frequency mixing method with harmonic rejection, the method comprising:
- generating an oscillator signal having a ⅓ duty cycle; and
- generating an output signal by mixing an input signal with the oscillator signal.
8. The frequency mixing method of claim 7, wherein the generating of the output signal comprises switching the input signal according to the oscillator signal.
9. The frequency mixing method of claim 7, wherein the input signal is a voltage signal, and
- wherein the generating of the output signal comprises:
- converting the input signal into a current signal by using a transconductance; and
- determining the current signal as the output signal if the oscillator signal is in an active state, and determining a predetermined value as the output signal if the oscillator signal is in an inactive state.
10. The frequency mixing method of claim 7, wherein the generating of the oscillator signal comprises:
- generating a first oscillator signal having a ⅓ duty cycle; and
- generating a second oscillator signal having a ⅓ duty cycle and a same frequency as and an opposite phase to the first oscillator signal, and
- wherein the generating of the output signal comprises:
- generating a first mixed signal by mixing the input signal with the first oscillator signal;
- generating a second mixed signal by mixing the input signal with the second oscillator signal; and
- subtracting the second mixed signal from the first mixed signal.
11. The frequency mixing method of claim 10, wherein the generating of the first mixed signal comprises switching the input signal according to the first oscillator signal, and
- wherein the generating of the second mixed signal comprises switching the input signal according to the second oscillator signal.
12. The frequency mixing method of claim 10, wherein the input signal is a voltage signal,
- wherein the generating of the first mixed signal comprises:
- converting the input signal into a first current signal by using a first transconductance; and
- determining the first current signal as the first mixed signal if the first oscillator signal is in an active state, and determining a first predetermined value as the first mixed signal if the first oscillator signal is in an inactive state, and
- wherein the generating of the second mixed signal comprises:
- converting the input signal into a second current signal by using a second transconductance; and
- determining the second current signal as the second mixed signal if the second oscillator signal is in an active state, and determining a second predetermined value as the second mixed signal if the second oscillator signal is in an inactive state.
13. The frequency mixing method of claim 9, wherein the predetermined value is 0.
14. The frequency mixing method of claim 12, wherein the first predetermined value is 0,
- and wherein the second predetermined value is 0.
15. A ⅓ duty cycle oscillator apparatus comprising:
- an oscillator unit which generates a first through a fourth oscillator signal, each having a ½ duty cycle, a same predetermined frequency, and phases of 0°, 90°, 180°, and 270° respectively;
- a first division unit which generates a fifth oscillator signal having a ⅓ duty cycle and ⅓ the predetermined frequency of the first oscillator signal, by dividing the first oscillator signal by three;
- a second division unit which generates a sixth oscillator signal having a ⅓ duty cycle and ⅓ the predetermined frequency of the second oscillator signal, by dividing the second oscillator signal by three;
- a third division unit which generates a seventh oscillator signal having a ⅓ duty cycle and ⅓ the predetermined frequency of the third oscillator signal, by dividing the third oscillator signal by three; and
- a fourth division unit which generates an eighth oscillator signal having a ⅓ duty cycle and ⅓ the predetermined frequency of the fourth oscillator signal, by dividing the fourth oscillator signal by three,
- wherein the fifth through the eighth oscillator signals respectively each have phases of 0°, 270°, 180°, and 90°.
16. The ⅓ duty cycle oscillator apparatus of claim 15, further comprising:
- a reset signal generating unit which generates a reset signal according to an edge of the first oscillator signal, the second oscillator signal, the third oscillator signal, or the fourth oscillator signal,
- wherein operation of each of the first through the fourth division units is started according to the reset signal.
17. The ⅓ duty cycle oscillator apparatus of claim 16, wherein each of the first through the fourth division units starts to generate pulses of a corresponding generated oscillator signal if a predetermined number of edges of the corresponding divided oscillator signal are received, after operation is started according to the reset signal, and
- wherein the predetermined number is one of 1 through 3.
18. The ⅓ duty cycle oscillator apparatus of claim 17, wherein each of the first through the fourth division units comprises a first flip-flop, a second flip-flop, and a NOR gate,
- wherein for each of the first through the fourth division units, an output signal of the first flip-flop is used as an input signal of the second flip-flop,
- wherein for each of the first through the fourth division units, output signals of the first and second flip-flops are used as input signals of the NOR gate,
- wherein for each of the first through the fourth division units, an output signal of the NOR gate is used as an input signal of the first flip-flop,
- wherein for each of the first through the fourth division units, the reset signal is used as reset signals of the first and second flip-flops,
- wherein for each of the first through the fourth division units, the corresponding divided oscillator signal of each of the first through the fourth division units is used as clock signals of the first and second flip-flops, and
- wherein for each of the first through the fourth division units, the output signal of the first flip-flop, the second flip-flop, or the NOR gate is output as the corresponding generated oscillator signal of the corresponding division unit.
19. The ⅓ duty cycle oscillator apparatus of claim 18, wherein each of the first through the fourth division units uses the output signal of the first flip-flop of the corresponding division unit as the corresponding generated oscillator signal if the predetermined number is 1, uses the output signal of the second flip-flop of the corresponding division unit as the corresponding generated oscillator signal if the predetermined number is 2, and uses the output signal of the NOR gate of the corresponding division unit as the corresponding generated oscillator signal if the predetermined number is 3.
20. A ⅓ duty cycle oscillator signal generating method comprising:
- generating a first through a fourth oscillator signals, each signal having a ½ duty cycle, a same predetermined frequency, and phases of 0°, 90°, 180°, and 270° respectively;
- generating a fifth oscillator signal having a ⅓ duty cycle and ⅓ the predetermined frequency of the first oscillator signal, by dividing the first oscillator signal, by three;
- generating a sixth oscillator signal having a ⅓ duty cycle and ⅓ the predetermined frequency of the second oscillator signal by dividing the second oscillator signal, by three;
- generating a seventh oscillator signal having a ⅓ duty cycle and ⅓ the predetermined frequency of the third oscillator signal by dividing the third oscillator signal, by three; and
- generating an eighth oscillator signal having a ⅓ duty cycle and ⅓ the predetermined frequency of the fourth oscillator signal by dividing the fourth oscillator signal, by three,
- wherein the fifth through eighth oscillator signals respectively each have phases of 0°, 270°, 180°, and 90°.
21. The ⅓ duty cycle oscillator signal generating method of claim 20, further comprising generating a reset signal according to an edge of the first oscillator signal, the second oscillator signal, the third oscillator signal, or the fourth oscillator signal,
- wherein each of the generating of the fifth oscillator signal, the generating of the sixth oscillator signal, the generating of the seventh oscillator signal, and the generating of the eighth oscillator signal is started according to the reset signal.
22. The ⅓ duty cycle oscillator signal generating method of claim 21, wherein each of the generating of the fifth oscillator signal, the generating of the sixth oscillator signal, the generating of the seventh oscillator signal, and the generating of the eighth oscillator signal comprises:
- starting to generate pulses of the corresponding generated oscillator signal if a predetermined number of edges of the corresponding divided oscillator signal are received, after the generating is started according to the reset signal, and
- wherein the predetermined number is one of 1 through 3.
23. A ⅓ duty cycle oscillator apparatus comprising:
- an oscillator unit generating a first and a second oscillator signal, each having a ½ duty cycle, a same predetermined frequency, and opposite phases;
- a first division unit generating a third oscillator signal having a ⅓ duty cycle and ⅓ the predetermined frequency of the first oscillator signal, by dividing the first oscillator signal by three; and
- a second division unit generating a fourth oscillator signal having a ⅓ duty cycle and ⅓ the predetermined frequency of the second oscillator signal, by dividing the second oscillator signal by three,
- wherein the third and fourth oscillator signals have opposite phases.
24. The ⅓ duty cycle oscillator apparatus of claim 23, further comprising a reset signal generating unit which generates a reset signal according to an edge of the first oscillator signal or an edge of the second oscillator signal,
- wherein operation of each of the first and the second division units is started according to the reset signal.
25. The ⅓ duty cycle oscillator apparatus of claim 24, wherein each of the first and the second division units starts to generate pulses of the corresponding generated oscillator signal if a predetermined number of edges of the corresponding divided oscillator signal are received by the corresponding division unit, after operation of the corresponding division unit is started according to the reset signal, and
- wherein the predetermined number is one of 1 through 3.
26. The ⅓ duty cycle oscillator apparatus of claim 25, wherein each of the first and the second division units comprises a first flip-flop, a second flip-flop, and a NOR gate,
- wherein for each of the first and the second division units, an output signal of the first flip-flop is used as an input signal of the second flip-flop,
- wherein for each of the first and the second division units, output signals of the first and the second flip-flops are used as input signals of the NOR gate,
- wherein for each of the first and the second division units, an output signal of the NOR gate is used as an input signal of the first flip-flop,
- wherein for each of the first and the second division units, the reset signal is used as reset signals of the first and the second flip-flops,
- wherein for each of the first and the second division units, the corresponding divided oscillator signal of each of the first and the second division units is used as clock signals of the first and second flip-flops, and
- wherein for each of the first and the second division units, the output signal of the first flip-flop, the second flip-flop, or the NOR gate is used as the corresponding generated oscillator signal of the corresponding division unit.
27. The ⅓ duty cycle oscillator apparatus of claim 26, wherein each of the first and the second division units uses the output signal of the corresponding first flip-flop as the corresponding generated oscillator signal if the predetermined number is 1, uses the output signal of the corresponding second flip-flop as the corresponding generated oscillator signal if the predetermined number is 2, and uses the output signal of the corresponding NOR gate as the corresponding generated oscillator signal if the predetermined number is 3.
28. A ⅓ duty cycle oscillator signal generating method comprising:
- generating a first and a second oscillator signal, each signal having a ½ duty cycle, a same predetermined frequency, and opposite phases;
- generating a third oscillator signal having a ⅓ duty cycle and ⅓ the predetermined frequency of the first oscillator signal, by dividing the first oscillator signal by three; and
- generating a fourth oscillator signal having a ⅓ duty cycle and ⅓ the predetermined frequency of the second oscillator signal, by dividing the second oscillator signal by three;
- wherein the third and fourth oscillator signals have opposite phases.
29. The ⅓ duty cycle oscillator signal generating method of claim 28, further comprising generating a reset signal according to an edge of the first oscillator signal or an edge of the second oscillator signal,
- wherein each of the generating of the third oscillator signal and the generating of the fourth oscillator signal is started according to the reset signal.
30. The method of claim 29, wherein each of the generating of the third oscillator signal and the generating of the fourth oscillator signal comprises starting to generate pulses of the corresponding generated oscillator signal if a predetermined number of edges of the corresponding divided oscillator signal are received, after the generating is started according to the reset signal, and
- wherein the predetermined number is one of 1 through 3.
Type: Grant
Filed: Dec 16, 2009
Date of Patent: Jul 26, 2011
Patent Publication Number: 20110006849
Assignees: Samsung Electronics Co., Ltd. (Suwon-si), Korea Advanced Institute of Science and Technology (Daejeon)
Inventors: Sang-sung Lee (Daejeon), Sang-gug Lee (Daejeon)
Primary Examiner: David Mis
Attorney: Sughrue Mion, PLLC
Application Number: 12/639,601
International Classification: H03B 21/00 (20060101); H03B 21/01 (20060101); H03B 27/00 (20060101); H04B 1/26 (20060101); H04B 1/28 (20060101);