Patents Examined by David Nhu
  • Patent number: 9881919
    Abstract: A method for doping fins includes depositing a first dopant layer at a base of fins formed in a substrate, depositing a dielectric layer on the first dopant layer and etching the dielectric layer and the first dopant layer in a first region to expose the substrate and the fins. A second dopant layer is conformally deposited over the fins and the substrate in the first region. The second dopant layer is recessed to a height on the fins in the first region. An anneal is performed to drive dopants into the fins from the first dopant layer in a second region and from the second dopant layer in the first region to concurrently form punch through stoppers in the fins and wells in the substrate.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: January 30, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Effendi Leobandung, Tenko Yamashita
  • Patent number: 9780242
    Abstract: A polymer substrate and back contact structure for a photovoltaic element, and a photovoltaic element include a CIGS photovoltaic structure, a polymer substrate having a device side at which the photovoltaic element can be located and a back side opposite the device side. A layer of dielectric is optionally formed at the back side of the polymer substrate. A metal structure is formed at the device side of the polymer substrate.
    Type: Grant
    Filed: November 4, 2015
    Date of Patent: October 3, 2017
    Assignee: ASCENT SOLAR TECHNOLOGIES, INC.
    Inventors: Lawrence M. Woods, Hobart Stevens, Joseph H. Armstrong, Richard Thomas Treglio
  • Patent number: 9614081
    Abstract: A gate insulating film and a gate electrode of non-single crystalline silicon for forming an nMOS transistor are provided on a silicon substrate. Using the gate electrode as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source/drain region of the nMOS transistor, whereby the gate electrode is amorphized. Subsequently, a silicon oxide film is provided to cover the gate electrode, at a temperature which is less than the one at which recrystallization of the gate electrode occurs. Thereafter, thermal processing is performed at a temperature of about 1000° C., whereby high compressive residual stress is exerted on the gate electrode, and high tensile stress is applied to a channel region under the gate electrode. As a result, carrier mobility of the nMOS transistor is enhanced.
    Type: Grant
    Filed: July 5, 2016
    Date of Patent: April 4, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hirokazu Sayama, Kazunobu Ohta, Hidekazu Oda, Kouhei Sugihara
  • Patent number: 9601693
    Abstract: Methods of depositing silicon nitride encapsulation layers by atomic layer deposition over memory devices including chalcogenide material are provided herein. Methods include using iodine-containing silicon precursors and depositing thermally using ammonia or hydrazine as a second reactant, or iodine-containing silicon precursors and depositing using a nitrogen-based or hydrogen-based plasma.
    Type: Grant
    Filed: November 6, 2015
    Date of Patent: March 21, 2017
    Assignee: Lam Research Corporation
    Inventors: Jon Henri, Dennis M. Hausmann, Seshasayee Varadarajan, Bhadri N. Varadarajan
  • Patent number: 9601411
    Abstract: A semiconductor structure and a method for fabricating the same are provided. The semiconductor structure includes a wafer substrate having a top surface and a bottom surface, and a conductive pillar in the wafer substrate defined by a deep trench insulator through the top surface and the bottom surface of the wafer substrate. The method for fabricating the semiconductor structure includes following steps. A deep trench is formed from a top surface of a wafer substrate to define a conductive region in the wafer substrate. The conductive region is doped with a dopant. The deep trench is filled with an insulation material to form a deep trench insulator. And the wafer substrate is thinned from a bottom surface of the wafer substrate to expose the deep trench insulator and isolate the conductive region to form a conductive pillar.
    Type: Grant
    Filed: December 8, 2015
    Date of Patent: March 21, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Alexander Kalnitsky, Hsiao-Chin Tuan, Shih-Fen Huang, Hsin-Li Cheng, Felix Ying-Kit Tsui
  • Patent number: 9601501
    Abstract: An NVM array includes a plurality of NVM cells, a plurality of word lines extending along a first direction, a plurality of bit lines extending along a second direction, and a plurality of source lines. Each of the NVM cells includes a PMOS select transistor and a PMOS floating gate transistor serially connected to the PMOS select transistor. Each word line is electrically connected to the select gate of the PMOS select transistor. Each bit line is electrically connected to a doping region of the PMOS floating gate transistor of each of the plurality of NVM cells. Each source line is electrically connected to a doping region of the PMOS select transistor.
    Type: Grant
    Filed: May 16, 2016
    Date of Patent: March 21, 2017
    Assignee: eMemory Technology Inc.
    Inventors: Mu-Ying Tsao, Wei-Ren Chen
  • Patent number: 9595589
    Abstract: The present disclosure relates to a transistor device. In some embodiments, the transistor device has an epitaxial layer disposed over a substrate. The epitaxial layer is arranged between a source region and a drain region separated along a first direction. Isolation structures are arranged on opposite sides of the epitaxial layer along a second direction, perpendicular to the first direction. A gate dielectric layer is disposed over the epitaxial layer, and a conductive gate electrode is disposed over the gate dielectric layer. The epitaxial layer overlying the substrate improves the surface roughness of the substrate, thereby improving transistor device performance.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: March 14, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Hung Cheng, Cheng-Ta Wu, Yeur-Luen Tu, Chia-Shiung Tsai, Ru-Liang Lee, Tung-I Lin, Wei-Li Chen
  • Patent number: 9595647
    Abstract: Provided is a light emitting device, which includes a second conductive type semiconductor layer, an active layer, a first conductive type semiconductor layer, and a intermediate refraction layer. The active layer is disposed on the second conductive type semiconductor layer. The first conductive type semiconductor layer is disposed on the active layer. The intermediate refraction layer is disposed on the first conductive type semiconductor layer. The intermediate refraction layer has a refractivity that is smaller than that of the first conductive type semiconductor layer and is greater than that of air.
    Type: Grant
    Filed: February 11, 2015
    Date of Patent: March 14, 2017
    Assignee: LG INNOTEK CO., LTD.
    Inventor: Hyo Kun Son
  • Patent number: 9593420
    Abstract: A method and apparatus for manufacturing a lattice structure of a material on a substrate, wherein the process may be performed at atmospheric pressure, may not require a metallic substrate, may be capable of continuously generating the lattice structure as long as desired, may be as thin as a single layer of the lattice material, and may create the lattice structure with any material that is capable of being vaporized to create a stream of ionized particles and then condensed to form the lattice structure.
    Type: Grant
    Filed: November 9, 2015
    Date of Patent: March 14, 2017
    Inventor: Denton Jarvis
  • Patent number: 9593205
    Abstract: A polymer, an organic layer composition including the polymer, an organic layer formed from the organic layer composition, and a method of forming patterns using the organic layer composition, the polymer including a moiety represented by Chemical Formula 1: *-A1-A3A2-A4n*.
    Type: Grant
    Filed: November 9, 2015
    Date of Patent: March 14, 2017
    Assignee: SAMSUNG SDI CO., LTD.
    Inventors: Soo-Hyoun Mun, Hyo-Young Kwon, Seung-Hyun Kim, Ran Namgung, Dominea Rathwell, Hyeon-Il Jung, Yu-Mi Heo
  • Patent number: 9590156
    Abstract: The present invention provides a light-emitting diode (LED) package including: a substrate on which a set of bonding pads are formed; an LED element configured to provide light of a predetermined wavelength region, having a set of chip pads formed on a top surface thereof and being attached on a top surface of the substrate; a set of gold wires connecting the bonding pads of the substrate with the chip pads of the LED element; a phosphor layer formed in a cap shape having side and top portions of a uniform thickness and being configured to surround sides and a top surface of the LED element while being spaced apart therefrom; and a filler disposed to fill a space formed between the phosphor layer and the LED element, wherein the LED element, the gold wires, and the bonding pads of the substrate are under the phosphor layer cap.
    Type: Grant
    Filed: February 10, 2015
    Date of Patent: March 7, 2017
    Assignee: LIGHTIZER KOREA CO.
    Inventors: Jae Sik Min, Jae Young Jang, Jae Yeop Lee, Byoung Gu Cho
  • Patent number: 9583657
    Abstract: A polymer substrate and back contact structure for a photovoltaic element, and a photovoltaic element include a CIGS photovoltaic structure, a polymer substrate having a device side at which the photovoltaic element can be located and a back side opposite the device side. A layer of dielectric is optionally formed at the back side of the polymer substrate. A metal structure is formed at the device side of the polymer substrate.
    Type: Grant
    Filed: November 4, 2015
    Date of Patent: February 28, 2017
    Assignee: ASCENT SOLAR TECHNOLOGIES, INC.
    Inventors: Lawrence M. Woods, Hobart Stevens, Joseph H. Armstrong, Richard Thomas Treglio
  • Patent number: 9580803
    Abstract: A thin film deposition device and a method of depositing thin film materials are disclosed. In one aspect, the thin film deposition device includes a deposition chamber configured to accommodate a substrate and a first chamber plate placed in the deposition chamber and configured to mount the substrate on a first surface thereof. The thin film deposition device also includes a second chamber plate placed in the deposition chamber on the opposite side of the first chamber plate with reference to the substrate. A plurality of recesses are formed on a surface of the second chamber plate facing the first surface of the first chamber plate such that gas flow is formed through the respective recesses.
    Type: Grant
    Filed: November 4, 2015
    Date of Patent: February 28, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventors: Cheol Jang, Jin Koo Kang, Soo Youn Kim
  • Patent number: 9583348
    Abstract: Methods of treating metal-containing thin films, such as films comprising titanium carbide, with a silane/borane agent are provided. In some embodiments a film comprising titanium carbide is deposited on a substrate by an atomic layer deposition (ALD) process. The process may include a plurality of deposition cycles involving alternating and sequential pulses of a first source chemical that comprises titanium and at least one halide ligand, a second source chemical comprising metal and carbon, wherein the metal and the carbon from the second source chemical are incorporated into the thin film, and a third source chemical, wherein the third source chemical is a silane or borane that at least partially reduces oxidized portions of the titanium carbide layer formed by the first and second source chemicals. In some embodiments treatment forms a capping layer on the metal carbide film.
    Type: Grant
    Filed: January 4, 2016
    Date of Patent: February 28, 2017
    Assignee: ASM IP HOLDING B.V.
    Inventors: Jerry Chen, Vladimir Machkaoutsan, Brennan Milligan, Jan Maes, Suvi Haukka, Eric Shero, Tom Blomberg, Dong Li
  • Patent number: 9577167
    Abstract: A semiconductor light emitting device including a plurality of light emitting elements can be miniaturized while enabling to emit light with high luminance. The semiconductor light emitting device can include a mounting substrate, and a plurality of semiconductor light emitting elements mounted on the mounting substrate side by side, each of the semiconductor light emitting elements having a semiconductor structure layer that can include a first semiconductor layer of a first conductivity type, an active layer, and a second semiconductor layer of a second conductivity type opposite to the first conductivity type, which are layered in that order. Each of the semiconductor light emitting elements can have a resonator constituted by end surfaces of the semiconductor structure layer opposite to each other, and also has a recessed portion recessed from the surface of the second semiconductor layer toward the active layer.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: February 21, 2017
    Assignee: STANLEY ELECTRIC CO., LTD.
    Inventor: Tatsuma Saito
  • Patent number: 9570341
    Abstract: One method includes forming a conductive feature in a dielectric layer on a substrate for a semiconductor device. A hard mask layer and an underlying etch stop layer are formed on the substrate. The hard mask layer and the underlying etch stop layer are then patterned. The patterned etch stop layer is disposed over the conductive feature. At least one of the patterned hard mask layer and the patterned etch stop layer are used as a masking element during etching of a trench in the dielectric layer adjacent the conductive feature. A cap is then formed over the etched trench. The cap is disposed on the patterned etch stop layer disposed on the conductive feature.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: February 14, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Yuan Ting, Jyu-Horng Shieh
  • Patent number: 9564495
    Abstract: A semiconductor device includes a semiconductor body with parallel first and second surfaces and containing hydrogen-related donors. A concentration profile of the hydrogen-related donors vertical to the first surface includes a maximum value of at least 1E15 cm?3 at a first distance to the first surface and does not fall below 1E14 cm?3 over at least 60% of an interval between the first surface and the first distance.
    Type: Grant
    Filed: March 25, 2016
    Date of Patent: February 7, 2017
    Assignee: Infineon Technologies AG
    Inventors: Johannes Georg Laven, Hans-Joachim Schulze, Moriz Jelinek, Werner Schustereder
  • Patent number: 9559104
    Abstract: A mask read-only memory array is provided. The mask read-only memory array includes a semiconductor substrate having a surface; and a heavily doped layer formed on the surface of semiconductor substrate. The mask read-only memory array also includes a plurality of lightly doped discrete regions formed on the heavily doped layer, and a metal silicide layer formed on the lightly doped discrete regions. Wherein the metal silicide layer and the plurality of reverse type lightly doped discrete regions form a plurality of Schottky diode memory cells. Further, the mask read-only memory array includes conductive vias formed one a partial number of the plurality of Schottky diode memory cells for applying column selecting voltage to select certain memory cells.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: January 31, 2017
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Chao Zhang
  • Patent number: 9559126
    Abstract: An array substrate and a display including the array substrate, the array substrate includes a substrate (1); a pixel structural layer formed on the substrate (1); and a wiregrid layer (6) located between the substrate (1) and the pixel structural layer. The wiregrid layer (6) includes a plurality of light blocking bars (4) arranged in parallel. With the wiregrid layer (6) formed of light blocking bars (4), an occurrence of light leak due to a stress generated by the substrate (1) can be avoided.
    Type: Grant
    Filed: April 29, 2014
    Date of Patent: January 31, 2017
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Ki Man Kim, Jaegeon You
  • Patent number: 9559034
    Abstract: Methods and apparatuses for forming a package for high-power semiconductor devices are disclosed herein. A package may include a plurality of distinct thermal spreader layers disposed between a die and a metal carrier. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: January 31, 2017
    Assignee: Qorvo US, Inc.
    Inventors: Tarak A. Railkar, Deep C. Dumka