Abstract: A memory device is provided. The memory device includes a plurality of stack structures, a plurality of first stepped contacts, and a plurality of second stepped contacts. Each of the stack structures extends in a first direction, and includes a first semiconductor layer and a second semiconductor layer. The second semiconductor layer is disposed above the first semiconductor layer. Each of the first stepped contacts extends in a second direction, and a bottom surface thereof is electrically connected to the first semiconductor layers of an i+1th stack structure and an i+2th stack structure, wherein i is an odd number. Each of the second stepped contacts extends in the second direction, and a bottom surface thereof is electrically connected to the second semiconductor layers of an nth stack structure and the i+1th stack structure. The first direction is different from the second direction.

Abstract: The embodiments of the present invention provide a display substrate and a manufacturing method thereof, as well as a display device including the display substrate. The display substrate may include a base substrate and a thin film transistor arranged on the base substrate, the thin film transistor having a gate, a gate insulating layer, an oxide semiconductor active layer as well as a source electrode and a drain electrode arranged on the base substrate sequentially; the display substrate may further include an ultraviolet blocking layer, the ultraviolet blocking layer having a first portion arranged between the base substrate and the oxide semiconductor active layer. By arranging the ultraviolet blocking layer, the influence of ultraviolet light on the oxide semiconductor active layer can be mitigated or avoided.

Abstract: A method for fabricating an intermediate member of an electronic element, comprises: preparing a glass substrate as a support substrate having a first surface; forming a first inorganic film that contains silicon and has a second surface and a third surface opposite to the second surface, in such a manner that the first surface of the support substrate is in contact with the second surface of the first inorganic film; forming a first polyimide film containing fluorine on the third surface of the first inorganic film; and forming a second inorganic film containing silicon on the first polyimide film.

Abstract: According to one embodiment, a pattern formed through light exposure is observed under two or more different optical conditions, and a focus shift and exposure amount in the light exposure are estimated based on a brightness value of the pattern under each of the optical conditions.

Abstract: A nonvolatile memory (NVM) cell includes a semiconductor substrate having therein an N well and a P well; a first oxide define (OD) region and a second oxide define (OD) region disposed within the N well; a PMOS select transistor disposed on the first OD region; a PMOS floating gate transistor serially connected to the select transistor and being disposed on the on the first OD region, wherein the PMOS floating gate transistor comprises a floating gate overlying the first OD region; and an assistant gate protruding from one distal end of the floating gate to one edge of the second OD region such that the assistant gate is capacitively coupled to the second OD region and the N well. The select transistor, the floating gate transistor and the assistant gate disposed on the same N well.

Abstract: A semiconductor device includes first and second fin-shaped silicon layers on a substrate, each corresponding to the dimensions of a sidewall pattern around a dummy pattern. First and second pillar-shaped silicon layers reside on the first and second fin-shaped silicon layers, respectively. An n-type diffusion layer resides in an upper portion of the first fin-shaped silicon layer and in upper and lower portions of the first pillar-shaped silicon layer. A p-type diffusion layer resides in an upper portion of the second fin-shaped silicon layer and upper and lower portions of the second pillar-shaped silicon layer. First and second gate insulating films and metal gate electrodes are around the first and second pillar-shaped silicon layers, respectively. A metal gate line is connected to the first and second metal gate electrodes and extends in a direction perpendicular to the first and second fin-shaped silicon layers.

Abstract: A power integrated device includes a drift region disposed in a substrate, a source region disposed in the substrate spaced apart from the drift region, a drain region disposed in the drift region, a gate insulation layer and a gate electrode sequentially stacked on the substrate between the source region and the drift region, a trench isolation layer disposed in the drift region adjacent to a side of the drain region, and a deep trench field insulation layer disposed in the drift region adjacent to another side of the drain region, wherein a vertical height of the deep trench field insulation layer is greater than a width of the deep trench field insulation layer.

Abstract: A technique for forming an integrated circuit die that contains an integrated sensor is provided. The integrated circuit die may be configured such that the sensor is exposed to ambient environmental conditions such that the sensor may detect ambient conditions. The integrated circuit die may be generally protected from environmental exposure by a mold resin. The mold resin may be formed in areas outside of a sensor region. Resin bleed from the mold resin into the sensor region may be prevented by the use of a resin dam that extends from the surface of the integrated circuit die. The resin dam may surround the sensor region.

Abstract: Gang clips (500) having a flat area (510), a ridge (510a), and tie bars (530b) extending from the flat area, the end portions of the ties bars aligned in a common x-direction; a plurality of gang clips having respective end portions of tie bars merged in x-direction to form an elongated chain (701) of clips; and a plurality of chains arrayed parallel to each other, free of tie bars between adjacent chains, the plurality having the chain ends tied at both ends (730a) to rails (740) normal to the chains to form a matrix (700) of clips having the rails as a stable frame.

Abstract: The invention generally related to a method for preparing a layer of graphene directly on the surface of a substrate, such as a semiconductor substrate. The layer of graphene may be formed in direct contact with the surface of the substrate, or an intervening layer of a material may be formed between the substrate surface and the graphene layer.

Abstract: Disclosed are composites that include a matrix and at least one filler. The matrix may be a core-shell particle assembly that includes an inorganic core and a polymeric shell. The refractive index of the core may be adjusted by adjusting the volume fraction of the core, such that the refractive index of the core-shell particle assembly matches or substantially matches the refractive index of the filler. Optically transparent composites that exhibit properties of the filler may therefore be achieved. Methods of making such composites and light sources including such composites are also disclosed.

Abstract: The invention generally related to a method for preparing a layer of graphene directly on the surface of a semiconductor substrate. The method includes forming a carbon-containing layer on a front surface of a semiconductor substrate and depositing a metal film on the carbon layer. A thermal cycle degrades the carbon-containing layer, which forms graphene directly upon the semiconductor substrate upon cooling. In some embodiments, the carbon source is a carbon-containing gas, and the thermal cycle causes diffusion of carbon atoms into the metal film, which, upon cooling, segregate and precipitate into a layer of graphene directly on the semiconductor substrate.

Abstract: An image sensor is provided. The image sensor includes a semiconductor substrate having a sensing region and a non-sensing region; a passivation layer formed on the semiconductor substrate; a first planar layer formed on the passivation layer; a color filter layer formed on the first planar layer with respect to the sensing region and a shielding layer formed on the first planar layer with respect to the non-sensing region; a plurality of micro-lens layers formed on the color filter layer and on the shielding layer; and a plurality of cap oxide layers formed on the micro-lens layer.

Abstract: A semiconductor package includes at least one semiconductor die having an active surface, an interposer element having an upper surface and a lower surface, a package body, and a lower redistribution layer. The interposer element has at least one conductive via extending between the upper surface and the lower surface. The package body encapsulates portions of the semiconductor die and portions of the interposer element. The lower redistribution layer electrically connects the interposer element to the active surface of the semiconductor die.

Abstract: Embodiments of a photodiode array are provided herein. In some embodiments, a photodiode array may include a semiconductor layer configured to convert photons into analog electrical signals; and a passive layer having a first surface and a second surface disposed opposite the first surface, wherein the semiconductor layer is coupled to the first surface, and wherein the passive layer is configured to have a signal receiving component coupled directly to the second surface of the passive layer.

Abstract: A backside illuminated image sensor having a photodiode and a first transistor in a sensor region and located in a first substrate, with the first transistor electrically coupled to the photodiode. The image sensor has logic circuits formed in a second substrate. The second substrate is stacked on the first substrate and the logic circuits are coupled to the first transistor through bonding pads, the bonding pads disposed outside of the sensor region.

Abstract: The present invention allows a current leakage path to be reliably disconnected even when a conductive film residue occurs between data wiring lines. An interlayer insulating film of a TFT panel includes an interlayer insulating film opening at a position corresponding to a pattern edge of an insulating protective film.

Abstract: Discussed is an array substrate for a display device, that may include a plurality of cell portions each including a display area and a non-display area except the display area, the display area having a plurality of pixels, first and second cell portions each including the plurality of cell portions, and a shorting bar surrounding the first cell portion and the second portion and disposed therebetween, wherein the display area includes pixel electrodes respectively formed in the plurality of pixels and a common electrode formed on the pixel electrodes, the common electrode being formed throughout entire the display area.

Abstract: Methods of fabricating transistors having raised active region(s) with at least partially angled upper surfaces are provided. The method includes, for instance: providing a gate structure disposed over a substrate, the gate structure including a conformal spacer layer; forming a raised active region adjoining a sidewall of the conformal spacer layer; providing a protective material over the raised active region; selectively etching-back the sidewall of the conformal spacer layer, exposing a side portion of the raised active region below the protective material; and etching the exposed side portion of the raised active region to partially undercut the protective material, wherein the etching facilitates defining, at least in part, an at least partially angled upper surface of the raised active region of the transistor.

Abstract: An integrated antenna package including a laminated structure and a multi-layered substrate is provided. The laminated structure includes at least a chip embedded therein and at least a plated through-hole structure penetrating the laminated structure. The multi-layered substrate is stacked on the laminated structure. The multi-layered substrate includes at least a metal layer located on one side of the multi-layered substrate away from the laminated structure and the metal layer includes at least an antenna pattern located above the chip. The multi-layered substrate includes at least a plated via and through-hole structure penetrating the multi-layered substrate and electrically connected to the chip, so that the antenna pattern is electrically connect with the chip. Also, the manufacturing method of the integrated antenna package is provided.