Abstract: A new GaAs FET structure is provided by a process which provides a GaAs channel between AlGaAs layers and wherein the GaAs channel has a higher active carrier concentration than either adjacent AlGaAs layer.

Abstract: Implantation of a Group V ion species (e.g., phosphorus or arsenic) into an In-based Group III-V compound semiconductor (e.g., InP, InGaAs) followed by implantation of Be ions produces a shallow p-type surface layer and avoids significant in-diffusion of the dopant species. High carrier concentrations and activation efficiences are attained. The technique has application in the fabrication of FETs, APDs and ohmic contacts.

Abstract: A method and resulting circuit structure (10) are disclosed for sputtering metallic silicide gates (18) on gallium arsenide integrated circuit structures. Silicon and metallic layers (14,15,14') are sputtered onto a gallium arsenide substrate (12) for stable high-temperature gate metallizations on VLSI structures.

Abstract: A semiconductor device referred to as complementary metal electrode semiconductor (CMES) has p-type and n-type silicon MESFETs interconnected on a substrate with an n-type barrier enhancement implanted into the p-channel of the p-type MESFET. The structure and method of fabrication are provided for forming a CMES logic inverter which has characteristics of very low power, low voltage, low noise and high speed.

Abstract: A compound field-effect transistor has a substrate with an epitaxial layer formed thereon. The layer includes two planar-doped layers, each of which is one approximately atom thick and is formed by atomic-planar-doping in two dimensions. The space separating the two planar-doped layers is equal to or less than a mean free path of electrons. A large majority of the carrier electrons are present at the center of the space between the two planar-doped electrons, which suppresses the scattering of impurity ions. As a result, there is an ultra-high-speed transistor.

Abstract: A semiconductor apparatus having a region for isolation between devices comprises a semiconductor substrate, a polycrystalline silicon layer portions selectively formed to be spaced apart from each other on the semiconductor substrate, an impurity diffused region formed under the polycrystalline silicon layer, and a silicon oxide film for filling in a space between the respective adjacent portions of the polycrystalline silicon layer. The impurity diffused region constitutes a source or drain region of a field effect device such as a MOS transistor isolated by the silicon oxide film.

Abstract: The threshold of a double diffused insulated gate field effect transistor is determined by selectively positioning the source in the decreasing impurity concentration region of the body to set the peak impurity concentration in the channel region for the desired threshold voltage without modification of the process.

Abstract: An input protector device for a semiconductor device such as a CMOS device, in which a first resistor is formed on an insulating film of a semiconductor substrate, and a second resistor is formed of an impurity diffusion region in the substrate, the first and second resistors and a capacitor being coupled to one another in series to constitute a filter circuit, and in which first and second diodes each cooperated with at least one of the first and second resistors, by-passing noises having low and high voltages, respectively, and a high frequency noise is cut by the filter circuit, thereby effectively preventing latchup.

Abstract: A strip for carrying a plurality of small size electronic parts such as LEDs enclosed hermetically in resin and a method of manufacturing the same. A grid-like conductor strip member is formed by interconnecting lead wires for the electronic parts in a grid-like pattern. The conductor strip member is partially embedded within resin to form a strip segment in which the plurality of electronic parts are mutually connected by runner member. The strip segment has a connecting portion formed integrally at least at one end thereof. By connecting together continuously a number of the strip segments by means of the connecting portions through repetitive cycles of molding operation, the electronic part carrying strip of any desired length up to a semi-endless length can be manufactured.

Abstract: A self-aligned metallization for an MOS device is described in which a first layer of tungsten is selectively deposited on the exposed silicon surfaces of the device including at least the source, drain and gate regions of the device, a layer of material providing nucleation sites for tungsten is selectively formed across insulating oxide regions of the device, and a second tungsten layer is selectively deposited on the nucleating layer and the exposed first tungsten layer to provide interconnection across the oxide regions. In addition to having a low electrical resistivity, such a metallization enables relaxed mask alignment and etching tolerance requirements, and is therefore useful in VLSI circuits.

Abstract: A channel surface with a channel region and a gate electrode opposing to each other is formed approximately vertical to a main surface of a semiconductor substrate in the field effect transistor (FET). A p type (n type) single crystal silicon layer is formed in a hole of an insulating layer on the main surface of the substrate. N type (p type) drain and source regions are formed defining the channel region in the single crystal silicon layer. A gate electrode is formed above the channel region on the side wall of the single crystal silicon layer in the hole. The area of the main surface of the substrate occupied by one FET can be reduced in this manner. A semiconductor device can be provided in which FETs are integrated to a higher degree without degrading performance of the transistors.

Abstract: A semiconductor imaging element for generating an electrical signal representing the intensity of incident light includes an avalanche photodiode, having sequential p-type, intrinsic, and n-type layers, with a compositional superlattice as the intrinsic layer, for converting incident light to an electric signal, and a switch electrically connected to the photodiode for receiving and reading out the signal. The photodiode and switch are disposed at least partially overlying each other on the same substrate. A two-dimensional array of the imaging element can be used to generate an electrical signal representing a two-dimensional picture of a material object.

Abstract: A vertical MOSFET device has a first conductivity type substrate layer serving as a drain, a second conductivity type channel region extending into said substrate layer from a top surface, and a first conductivity type source region extending into the channel region from the top surface. The channel region has a peripheral subregion extending deeply into the substrate layer from the top surface under an insulated gate electrode, and a shallow central subregion shallower than the peripheral subregion. There is further provided a second conductivity type underlying layer formed under the shallow central subregion so as to form a voltage regulating diode with the channel region at a position shallower than the bottom of the peripheral subregion.

Abstract: An improved pin junction photovoltaic element which causes photoelectromotive force by the junction of a p-type semiconductor layer, an i-type semiconductor layer and an n-type semiconductor layer, characterized in that at least one of said p-type semiconductor layer and said n-type semiconductor layer comprises a p-typed or n-typed ZnSe:H:M film, where M is a dopant of p-type or n-type: the amount of the H is in the range of from 1 to 4 atomic %: and said film contains crystal grain domains in a proportion of 65 to 85 vol % per unit volume; and said i-type semiconductor layer comprises a non-single crystal Si(H,F) film or a non-single crystal Si(C,Ge)(H,F) film.

Abstract: In a MIS transistor device, a gate electrode is formed on a first conductivity-type well region formed in a semiconductor substrate. By implanting impurities with the gate electrode and an element-isolating region made up of a field insulating film as a mask, an N-type diffusion layer having a higher impurity concentration than the first conductivity-type well region is formed on the sides of the gate electrode. A second conductivity-type diffusion layer of a first impurity concentration higher than the N-type diffusion layer is formed with a smaller width than the N-type diffusion layer in the N-type diffusion layer formed on one side of the gate electrode. A second conductivity-type diffusion layer of a second high concentration is formed with a smaller width than the N-type diffusion layer in the N-type diffusion layer formed on the other side of the gate electrode.

Abstract: The present invention provides a surface mount Gull-Wing type resin-encapsulating package for encapsulating a semiconductor chip, wherein the cut face (outer tip end) of each outer lead is formed to have a smaller cross-sectional area than that of each outer lead, for improving the extension of solder to the cut face of that lead. Such relatively smaller cross-sectional area of the outer tip end of each outer lead reduces the exposed area of the lead material when disconnecting the leads from the frame in separating the device from the frame.

Abstract: A semiconductor device includes trench capacitors formed in a semiconductor substrate, a trench provided therebetween for isolating the trench capacitors, and a trench capacitor formed in a side wall of the trench for isolating the trench capacitors.

Abstract: An integrated circuit is formed in a semiconductor die having a front face and a back face, the die having at least first and second functional regions. The first functional region comprises at least one zone of p-type material and at least one zone of n-type material that meets the zone of p-type material in a p-n junction. The integrated circuit comprises connection pads connected respectively to the zone of p-type material and the zone of n-type material, whereby those zones can be connected to an external circuit. At least one of the connection pads is electrically isolated from the second functional region of the integrated circuit. The integrated circuit is treated by mounting the die on a support member and removing material of the die so as to separate the functional regions of the die from each other.

Abstract: An insulated gate field effect transistor, in which at least the drain region is surrounded by an impurity region of the same conductivity type as and a higher impurity concentration than the substrate, is disclosed. A portion of the impurity region under the drain region contains both of P-type and N-type impurities to form an abrupt profile therby depleting the portion with a depletion layer by the built-in potential.

Abstract: Thin-film photodiodes arranged in lines on a substrate are connected to read-out chips arranged on the same substrate. They are connected thereto via thin-film interconnects which differ in length and which run parallel to one another. For compensating the interconnect capacitances given neighboring interconnects which differ in length, their widths are dimensioned smaller or larger in one or more interconnect sub-sections. Thus, the sum of the coupling capacitances of all sub-sections of two neighboring interconnects always have the same value, independently of the overall length. The invention eliminates the inhomogeneities in the sensor signal caused by the different lengths of the read-out lines. The invention is employed for opto-electronic reading equipment, particularly in office automation.