Abstract: A field effect transistor has its channel region and source drain regions extending in a direction approximately vertical to a main surface of a substrate. The field effect transistor may be a complementary type in which p type and n type transistors are formed as a pair. The channel region and the source drain regions may be placed side by side in the direction of the main surface of the substrate or they may be placed side by side in the direction of the depth of the substrate. In such transistors, each of the regions is formed by stepup implantation carried out by stepup voltage of the corresponding ion beam.

Abstract: A layer structure of a memory cell for a dynamic random access memory device includes a semiconductor substrate, an insulation film formed on the semiconductor substrate having a first window through which a surface of the semiconductor substrate is partially exposed, a first conductive film formed on the insulation film so as to surround the contact window and form a second window above the first window, a second conductive film formed so as to be in contact with the first conductive film, and the semiconductor substrate through the first and second windows, the first and second conductive films constructing a storage electrode of a memory cell capacitor, a dielectric film formed so as to cover the storage electrode; and a third conductive film formed so as to cover the dielectric film.

Abstract: Disclosed is a matrix of photosensitive elements for imaging. This matrix comprises, in series between a row conductor and a column conductor, a capacitor in series with a NIPIN or PINIP type phototransistor. This phototransistor can be made conductive, for the reading of the charges stored in the memory, as easily as a photodiode, even in darkness. The phototransistor is preferably formed by a stacking of N type, intrinsic type, P type, intrinisic type and N type semiconducting layers.

Abstract: A CMOSLSI is disclosed which includes a semiconductor body, a first N-well region formed in the semiconductor body, a second N-well region, a greater part of which is formed in the first N-well region, a first P-well region formed in the semi-conductor body, a second P-well region, a greater part of which is formed in the first P-well region, a P-channel MOS transistor formed in the second N-well region, and an N-channel MOS transistor formed in the second P-well region, to reduce the distance between the P-channel MOS transistor and the N-channel MOS transistor, thereby increasing the packing density of the CMOSLSI.

Abstract: In a semiconductor arrangement having at least one semiconductor body located on an insulating substrate provided with interconnects, a low-inductance arrangement can be achieved in that the connecting leads are arranged in close proximity to one another and at least partially parallel to one another.

Abstract: A semiconductor region that is inserted into a semiconductor member is provided, the latter being separated from the former by a planar pn junction including a first, more highly doped sub-region and a second, more lightly doped sub-region that is limited by a part of the pn junction that gradually approaches a boundary surface of the semiconductor member. An electrode contacts the semiconductor region and covers a part of the second sub-region and extends toward the lateral limitation of the semiconductor region to such an extent that, given the application of a voltage inhibiting the pn junction the space charge zone forming thereat has its edge lying in the boundary surface just reaching the electrode edge given a reduced breakdown voltage.

Abstract: A semiconductor device such as a semiconductor laser device or a transistor which is small in both threshold current and leakage current and exhibits no increase with time in the threshold current and leakage current can be obtained by incorporating pnp or npn junctions in a buried layer which coats an active region containing InGaAsP, forming the mid layer of the junctions with InGaAsP, adjusting the conductivity type of the mid layer with an implanted ion and specifying the energy band width of a semiconductor constituting the mid layer.

Abstract: In a Schottky gate field effect transistor comprising a channel formed by doping donor ions in the surface layer of a compound semiconductor (e.g., GaAs) substrate and performing heat treatment, a Schottky gate electrode formed over the channel, and a source electrode and a drain electrode formed on the respective sides of the Schottky gate electrode, a first and a second regions are formed by implantation of ions which are to become carrier killers, to have respective concentration peaks shallower and deeper than the concentration peak of the donor ions of the channel.

Abstract: Improved tape automated bonding (TAB) packaging technology is disclosed having particular utility with semiconductor integrated circuit chips having high gate count and I/O requirements, utilizing a polymer layer of the package to support decoupling capacitor(s) mounted across power and ground leads connecting the chip and internal planes of a printed circuit board to which the TAB package is attached.

Abstract: Integrated circuits with vertical isolated trenches are radiation hardened by providing vertical gate segments, preferably, of doped polycrystalline silicon, in the trenches and connected at the bottom of the trenches to a region of the same conductivity type. The surface devices may be complementary and the vertical gates may also be complementarily doped. A method of fabrication is described for a single crystal wafer, as well as SOI.

Abstract: An IGBT and FET are integrated in a common semiconductor body and share common source/emitter, base and drift regions and an insulated gate electrode. The ON-resistance and turn-off time of this device can be controlled by connecting the drain and collector electrodes to one main terminal for the device with a resistor between either the drain region/drift region interface or the collector junction and the main terminal of the device.

Abstract: In a semiconductor memory integrated circuit device having a stacked capacitor cell, a first plate electrode and a first dielectric film are formed underneath a charge storage electrode a charge storage electrode, and a second dielectric film and a second plate electrode are formed over the charge storage electrode. The charge storage electrode has contact with the diffusion region through a contact hole penetrating the first dielectric material. The first and second plate electrodes are connected via a contact hole penetrating the first and second electric films outside the cell area. Because both the upper surface and the lower surface of the charge storage electrode are utilized for formation of the capacitor the size of the capacitor can be halved to produce the same capacitance.

Abstract: This invention relates generally to dynamic random access, semiconductor memory arrays and more specifically relates to an ultra dense dynamic random access memory array. It also relates to a method of fabricating such arrays using a plurality of etch and refill steps which includes a differential etching step which is a key step in forming insulating conduits which themselves are adapted to hold a pair of field effect transistor gates of the adjacent transfer devices of one device memory cells. The differential etch step provides spaced apart device regions and an insulation region of reduced height between the trenches which space apart the memory cells. The resulting structure includes a plurality of rows of vertically arranged field effect transistors wherein the substrate effectively acts as a counterelectrode surrounding the insulated drain regions of each of the one device memory cells. A pair of gates are disposed in insulating conduits which run perpendicular to the rows of memory cells.

Abstract: A semiconductor device having a light transparent window includes: a wall produced at an outer contour of a light receiving section on the surface of a semiconductor chip, the molding resin which is produced after a process of inserting the chip in a metal mold. The wall and the metal mold adhere with each other for producing a space between the chip and the metal mold so that a light transparent window is produced at a light introduction section in a separate position from the wall above the chip.

Abstract: In accordance with the teachings of this invention, resistors are fabricated in semiconductor devices utilizing a layer of semiconductor material having a preselected resistivity. Means are provided for electrically isolating the semiconductor region from the regions located beneath, and isolation to adjacent regions is provided by forming a groove. Resistance value of a particular resistor fabricated in accordance with the teachings of this invention is dependent, in a coarse fashion, on the length and width of the resistor, as well as the resistivity of the semiconductor material used to fabricate the resistor. However, the final resistance value is determined by the diffusion of high concentration isolation dopants which serve to accurately control the effective cross-sectional area of the resistor.

Abstract: A rectifier is fabricated from a P-N junction having a P-type semiconductor layer and an adjacent N-type semiconductor layer. A mesa structure is formed in at least one of said layers. Impurities are deposited at the top of the mesa to form a high concentration region in the surface thereof. The impurities are diffused from the top surface of the mesa toward the P-N junction, whereby the mesa geometry causes the diffusion to take on a generally concave shape as it penetrates into the mesa. The distance between the perimeter of the high concentration region and the wafer substrate is therefore greater than the distance between the central portion of said region and the wafer substrate, providing improved breakdown voltage characteristics and a lower surface field. Breakdown voltage can be measured during device fabrication and precisely controlled by additional diffusions to drive the high concentration region to the required depth.

Abstract: A CMOS device wherein the N-channel devices have n+ gates, and the P-channel devices have p+ gates. A TiN local interconnect system is used to connect the two types of gates, as well as providing connections to moat.

Abstract: A self-protected MOS gated device includes a PN junction disposed in an electrical path between the source electrode and the gate contact of the device and integrally formed with a DMOS cell of the device to protect the DMOS cell from surge voltages. The PN junction has conductivity characteristics selected to provide junction breakdown at a predetermined voltage level and at a predetermined location along the junction.

Abstract: A semiconductor memory device comprises four memory cells (4a, 6) arranged in point symmetry on a semiconductor substrate (1), and an insulating layer (10) covering the memory cells and having one contact hole (2) placed in the center of the point symmetry, with the contact hole enabling electrical connection to each of the memory cells.

Abstract: A semiconductor device includes a bipolar transistor having an emitter region of one conductivity type formed in a base region of the opposite conductivity type, the base region being provided in a collector region of the one conductivity type. A first insulated gate field effect transistor provides a gateable connection to the emitter region of the bipolar transistor while a second insulated gate field effect transistor provides a charge extraction path from the base region when the bipolar transistor is turned off. The first insulated gate field effect transistor includes a further region of the other conductivity type provided in the emitter region, and a source region of the one conductivity type formed in the further region and an insulated gate overlying a channel area comprising at least part of the further region to provide a gateable connection between the emitter region and the source region of the first insulated gate field effect transistor.