Patents Examined by David Soltz
  • Patent number: 4881112
    Abstract: In an integrated circuit device having a highly doped bottom substrate layer of a first conductivity type, a lightly doped top layer of the first conductivity type formed on the substrate layer, a vertical MOSFET formed in the lightly doped top layer and a second circuit component, such as a CMOS, formed in the lightly doped top layer, there are further provided a guard ring and a recombination layer for preventing latchup of the second component by preventing minority carriers from moving from the vertical MOSFET to the second component. The guard ring is formed in the lightly doped top layer between the vertical MOSFET and the second component, and made of a second conductivity type single crystal semiconductor, or a first conductivity type polycrystalline silicon or an insulating material such as SiO.sub.2.
    Type: Grant
    Filed: May 20, 1988
    Date of Patent: November 14, 1989
    Assignee: Nissan Motor Company, Limited
    Inventor: Tsutomu Matsushita
  • Patent number: 4879587
    Abstract: A fusible link is described. It comprises a semiconductor substrate, an electrically insulating layer on the substrate, a pair of conductor elements on the surface of the insulating layer opposite the substrate, and a fuse conductor layer on the surface of the insulating layer opposite the substrate electrically connecting the conductor elements. A cavity is formed in the insulating layer and the substrate adjacent the fuse conductor layer. The cavity has a configuration to provide a substantial reduction in the thermal conductivity cross-section between the fuse conductor layer and the substrate. Such substantial reduction is selected to enable a predetermined electrical power input to the fuse conductor layer to generate an open circuit in the layer. In a preferred form, the cavity has a configuration to form a bridge comprised of the fuse conductor layer and the portion of the insulating layer upon which the fuse conductor layer is disposed.
    Type: Grant
    Filed: November 13, 1986
    Date of Patent: November 7, 1989
    Assignee: Transensory Devices, Inc.
    Inventor: John H. Jerman
  • Patent number: 4878095
    Abstract: In a semiconductor device having a plurality of semiconductor layers of different composition, such as a hot electron transistor, in which respective layers are contacted to form a majority carrier injection electrode, a control electrode and a majority carrier extraction electrode, the layers forming the electrodes are separated from one another by separating layers or layer systems of different composition. These separating layers form potential barriers for the majority carriers. A problem with such known devices is that the layer forming the control electrode has to have a low resistance which has previously required a high doping concentration in this layer. This doping concentration however increases losses due to plasmon/phonon coupling and scattering and reduces the switching speed of the device.
    Type: Grant
    Filed: November 9, 1987
    Date of Patent: October 31, 1989
    Assignee: Wissenschaften e.V.
    Inventors: Simon J. Bending, Elmar Bockenhoff
  • Patent number: 4876581
    Abstract: For preventing a field effect transistor from the short-channel effects, there is disclosed a field effect transistor comprising a channel region and source/drain regions deviating from the central portion of the channel region in the lateral direction of the field effect transistor, a gate electrode covered with an insulating film intervenes between the source/drain regions, so that the channel length is increased in length.
    Type: Grant
    Filed: June 17, 1988
    Date of Patent: October 24, 1989
    Assignee: NEC Corporation
    Inventor: Toshiyuki Ishijima
  • Patent number: 4876580
    Abstract: A tunnel injection controlling type semiconductor device comprising a source semiconductor region having a certain conductivity type for supplying carriers, a drain semiconductor region for receiving the carriers, and a gate electrode for controlling the flow of these carriers. A highly-doped semiconductor region having a conductivity type opposite to that of the source semiconductor region is provided in contact with the source region or contained locally in the source region to cause tunnel injection of carriers. The potential level of this highly-doped region is varied by virtue of the static induction effect exerted by the voltage applied to the gate electrode which is provided at a site close to but separate from the highly-doped region, and to the drain semiconductor region.
    Type: Grant
    Filed: April 27, 1987
    Date of Patent: October 24, 1989
    Assignee: Zaiden Hojin Handotai Kenkyu Shinkokai
    Inventor: Jun-ichi Nishizawa
  • Patent number: 4873565
    Abstract: A metal stud (24) is provided for interconnecting levels of metallization separated by an insulator on a semiconductor slice (10). A lead (12) is coated with a refractory metal (14) and a platable metal cap (16). A photoresist (18 ) is then applied and a cavity (22) is formed within the photoresist (18 ). The cavity (22) is plated to form the stud (24). The stud (24) is clad with a corrosion resistant layer (28).
    Type: Grant
    Filed: November 2, 1987
    Date of Patent: October 10, 1989
    Assignee: Texas Instruments Incorporated
    Inventor: Bobby A. Roane
  • Patent number: 4872040
    Abstract: A vertical heterojunction equal area transistor and starting structure therefor is provided in which three epitaxial layers structure with wide band gap external layers and narrower band gap center layer is provided with peripheral impurity concentrations such that the area around the wide gap electrodes is high resistivity and the area around the center narrower gap region is high conductivity. A bipolar transistor of GaAs-Ge-GaAs is described.
    Type: Grant
    Filed: April 23, 1987
    Date of Patent: October 3, 1989
    Assignee: International Business Machines Corporation
    Inventor: Thomas N. Jackson
  • Patent number: 4868752
    Abstract: A method and apparatus for use with an automatic working vehicle for detecting a boundary between a treated area and an untreated area. A predetermined range of working area including the treated area and the untreated area is photographed by a camera. Image data output from the camera is differentiated with respect to pixel to pixel brightness variations, which is then compared with a threshold value to produce edge image data on an X-Y plane showing, as binarized, a plurality of pixels regarded as representing a point of transition between the untreated area and the treated area, and other pixels. The boundary is calculated from the edge image data by means of HOUGH-transformation.
    Type: Grant
    Filed: September 10, 1987
    Date of Patent: September 19, 1989
    Assignee: Kubota Ltd.
    Inventors: Yasuo Fujii, Masahiko Hayashi
  • Patent number: 4868627
    Abstract: A complementary semiconductor integrated circuit for absorbing a noise comprises an n-type semiconductor substrate maintained at a supply voltage, a p-type well maintained at the reference voltage potential, an n-type region formed in the n-type semiconductor substrate and connected to the supply voltage, a polysilicon layer formed on the n-type region through an insulating film and connected to the reference voltage, whereby a capacitance is formed by the n-type region and the polysilicon layer formed on the n-type region through the insulating film. A noise included in the supply voltage is absorbed by the capacitance.
    Type: Grant
    Filed: June 28, 1988
    Date of Patent: September 19, 1989
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Akira Yamada, Tsunenori Umeki
  • Patent number: 4868620
    Abstract: An integrated circuit in which a large potential can be maintained between the source of the device and the substrate on which this device and other devices are fabricated is described. The circuit employs a minority carrier sink region to remove minority carriers from the gate region of a MOS depletion device. The sink region is shielded from the substrate by a buried layer which prevents punch-through between the sink region and the substrate.
    Type: Grant
    Filed: July 14, 1988
    Date of Patent: September 19, 1989
    Assignee: Pacific Bell
    Inventors: James E. Kohl, Eric J. Wildi, Robert S. Scott, Deva N. Pattanaya, Michael S. Adler
  • Patent number: 4864369
    Abstract: A semiconductor light emitting heterostructure device is disclosed. The device comprises an n-type GaAs substrate, a first n-type laeyr of AlGaAs adjacent to the substrate, a second p-type light emitting AlGaAs layer adjacent to the first layer, and a third p-type AlGaAs layer suitable for bonding to an aluminum contact. The device starts with an n-type substrate which is more readily available and has a p-side up configuration which is more suitable for bonding to an aluminum contact.
    Type: Grant
    Filed: July 5, 1988
    Date of Patent: September 5, 1989
    Assignee: Hewlett-Packard Company
    Inventors: Wayne L. Snyder, Dennis C. DeFevere, Frank M. Steranka, Chin-Wang Tu
  • Patent number: 4858497
    Abstract: A hydraulic control system for a continuously variable transmission for an automotive vehicle, the transmission having a first and a second variable-diameter pulley provided on respective second shafts, a belt connecting the first and second pulleys, and a first and a second hydraulic cylinder for changing effective diameters of the pulleys. The system includes a first pressure regulating valve, a shift-control valve for applying the first line pressure to one of the cylinders, and a second pressure regulating valve for regulating a pressure of the fluid flowing from the other cylinder, and thereby establishing a second line pressure. The system further includes a control device for controlling the shift-control valve so that an actual speed ratio of the transmission coincides with a target speed ratio determined depending upon a running condition of the vehicle.
    Type: Grant
    Filed: July 20, 1987
    Date of Patent: August 22, 1989
    Inventor: Katsumi Kouno
  • Patent number: 4860088
    Abstract: A flexible beam lead tape having three layers having trace conductors, a dielectric and a ground plane. Vias extend through the dielectric layer at the first and second ends of the electrical conductors for providing versatile connections to either ends of the conductors. The ends of the conductors may be provided with electrical connections on either or both sides of the tape and may be connected by pressure contact or by bonding.
    Type: Grant
    Filed: September 14, 1987
    Date of Patent: August 22, 1989
    Assignee: Microelectronics and Computer Technology Corporation
    Inventors: Robert T. Smith, Chang-Hwa Chung
  • Patent number: 4858162
    Abstract: An attachment for a portable computer comprising a rigid case having an interface card that is adapted to attach to the portable computer's expansion slot at one end and is adapted to attach to a standard PC expansion card at the other end. The case has room to insert a standard expansion card of 2/3 length or less. The case is sufficiently small that it may be attached to the bottom of the portable computer and still fit inside the original carrying case.
    Type: Grant
    Filed: August 28, 1987
    Date of Patent: August 15, 1989
    Assignee: Connect Computer Company, Inc.
    Inventors: Thomas M. Kieffer, David J. Gaasedelen
  • Patent number: 4855809
    Abstract: An orthogonal chip mount system module (10) comprising a base module (12), an interconnect chip (14), orthogonal slots (16) and semiconductor chips (18) is provided. The interconnect chip (14) is fixed to the base module (12) by high thermal conductivity epoxy. The semiconductor chips (18) are interference fitted into the slots (16). Solder pads (20) on the semiconductor chips (18) are aligned with solder pads (22) on the interconnect chip (14) and the system module (10) is then heated to the reflow temperature of the solder forming joints (24).
    Type: Grant
    Filed: November 24, 1987
    Date of Patent: August 8, 1989
    Assignee: Texas Instruments Incorporated
    Inventors: Satwinder Malhi, Kenneth E. Bean, Charles C. Driscoll, Pallab K. Chatterjee
  • Patent number: 4851892
    Abstract: A standard cell array is disclosed having improved device isolation, customized metal routing under power busses, a gate array core cell having improved internal routing channels, and shared power busses. A fake gate is located adjacent a source of drain of a transistor within each cell, and is coupled to a supply voltage for isolating the transistors within each cell. Additional metallization strips partially overlap and extend between adjacent rows and columns, respectively, of the core cells for providing supply voltages thereto. Further metallization strips for conducting signals overlie the internal portion of the core cell and extend the entire length of the row or column of core cells.
    Type: Grant
    Filed: September 8, 1987
    Date of Patent: July 25, 1989
    Assignee: Motorola, Inc.
    Inventors: Floyd E. Anderson, Richard R. Hamzik
  • Patent number: 4848529
    Abstract: In an automatic transmission system in which a gear transmission and a clutch are electronically controlled so as to shift the transmission to the optimum gear position, the system comprises a first generator for generating a set of initial map data corresponding to the position of a selector, the initial map data being for determining an initial target gear position to which the gear should be initially shifted after the position of the selector is changed, and a second generator for generating a set of normal map data corresponding to the position of the selector, the normal map data being for determining a normal target gear position to which the gear should be shifted after the gear is shifted to the determined initial target position. One of the outputs of the first and second generators is selected and applied to a calculator in which the target gear position is calculated in accordance with the selected map data. The gear transmission is automatically shifted to the calculated gear position.
    Type: Grant
    Filed: September 11, 1987
    Date of Patent: July 18, 1989
    Assignee: Diesel Kiki Co., Ltd.
    Inventors: Kazumasa Kurihara, Kenji Arai
  • Patent number: 4847665
    Abstract: In the monolithic integration of HFET and DOES devices, a wide band gap carrier confining semiconductor layer is provided only at predetermined locations where DOES devices are desired. This layer is not provided at other predetermined locations where HFET devices are desired as it would constitute a shunt path which would degrade the high frequency operation of the HFET devices. The invention is particularly useful where monolithic integration of optical sources, optical detectors, and electronic amplifying or switching elements is desired.
    Type: Grant
    Filed: March 31, 1988
    Date of Patent: July 11, 1989
    Assignee: Northern Telecom Limited
    Inventor: Ranjit S. Mand
  • Patent number: 4845650
    Abstract: A portable ticket issuing system comprises a portable electric ticket issuing machine including a keyboard and electric power means for supplying power to the ticket issuing machine, in which the power means comprises a battery unit having a battery casing separate from the ticket issuing machine casing, and including a flexible cable means for electrically connecting the battery and ticket issuing machine, and including a belt support means for mounting the battery and its casing on an operator away from his front and without the operator holding it manually and further support means for mounting the ticket issuing machine on the operator away from his front in a non-operating position where it is located at the operator's side resting on his thigh and so that it allows the ticket issuing machine to be readily moved to an operating position in front of the operator without moving the battery unit and preferably without detaching it from the belt.
    Type: Grant
    Filed: August 5, 1987
    Date of Patent: July 4, 1989
    Assignee: Almex Control Systems Limited
    Inventors: Roger Meade, Paul Schofield, Michael C. Wright
  • Patent number: 4839837
    Abstract: A portable, three layered laptop computer assembly includes a keyboard member pivotably attached to an output member and provided with an intermediate display member. Upon opening the three members from a closed position with the members forming a regular cubic configuration, the keyboard and output members will be disposed with their bottom surfaces co-planar while the display member attached to the mount member is automatically positioned in a substantially vertical manner.
    Type: Grant
    Filed: October 27, 1987
    Date of Patent: June 13, 1989
    Inventor: Bo E. Chang