Abstract: A semiconductor device includes a substrate and a p-doped layer including a doped III-V material on the substrate. An n-type material is formed on or in the p-doped layer. The n-type layer includes ZnO. An aluminum contact is formed in direct contact with the ZnO of the n-type material to form an electronic device.

Abstract: A method of making a semiconductor switch device and a semiconductor switch device made according to the method. The method includes depositing a gate dielectric on a major surface of a substrate. The method also includes depositing and patterning a gate electrode on the gate dielectric. The method further includes depositing an oxide to cover the top surface and sidewall(s) of the gate electrode. The method also includes, after depositing the oxide, performing a first ion implantation process at a first implantation dosage for forming a lightly doped drain region of the switch device. The method further includes forming sidewall spacers on the sidewall(s) of the gate electrode. The method also includes performing a second ion implantation process at a second implantation dosage for forming a source region and a drain region of the semiconductor switch device. The second implantation dosage is greater than the first implantation dosage.

Abstract: A manufacturing method of a display device in an embodiment according to the present invention, the method includes forming a terminal electrode in a terminal part of a first substrate, forming a pixel electrode corresponding to each pixel in a pixel part of the first substrate, forming a first intermediate layer in a region including the terminal electrode of the terminal part, forming an organic layer above the pixel electrode in the pixel part, forming a counter electrode layer above the first substrate including the pixel part and the terminal part, forming a passivation layer above the counter electrode layer, arranging a second substrate opposing the pixel part and bonding the first substrate and the second substrate using a sealing member enclosing the pixel part, and removing the first intermediate layer, the counter electrode layer and the passivation layer in the terminal part.

Abstract: A method for forming a semiconductor device comprising forming a stack of nanowires, the stack including a first nanowire having a first length, and a second nanowire having a second length, the second nanowire arranged above the first nanowire, forming a sacrificial gate stack on the stack of nanowires, growing a source/drain region on the first, second nanowires, removing the sacrificial gate stack to expose channel regions of the first and second nanowires, and forming a gate stack over the channel regions.

Abstract: A method for producing a fluorescent material is provided. The method includes preparing fluorescent material particles that contain an alkaline earth metal aluminate having a composition represented by (Sr1?x,Eux)4Al14O25, where x satisfies 0.05?x?0.4, and a part of Sr may be substituted by at least one element selected from the group consisting of Mg, Ca, Ba, and Zn; causing the prepared fluorescent material particles to come into contact with a liquid medium containing water; removing at least a portion of the contacted liquid medium to obtain purified fluorescent material particles; causing a phosphate compound to adhere to surfaces of the purified fluorescent material particles to obtain fluorescent material particles to which the phosphate compound is adhered; and heat treating the fluorescent material particles to which the phosphate compound is adhered at 500° C. to 700° C.

Abstract: Circuit module designs that incorporate dual gate field effect transistors are implemented with fully depleted silicon-on-insulator (FD-SOI) technology. Lowering the threshold voltages of the transistors can be accomplished through dynamic secondary gate control in which a back-biasing technique is used to operate the dual gate FD-SOI transistors with enhanced switching performance. Consequently, such transistors can operate at very low core voltage supply levels, down to as low as about 0.4 V, which allows the transistors to respond quickly and to switch at higher speeds. Performance improvements are shown in circuit simulations of an inverter, an amplifier, a level shifter, and a voltage detection circuit module.

Abstract: A system, method, and apparatus for an avalanche photodiode with an enhanced multiplier layer are disclosed herein. In particular, the present disclosure teaches an avalanche photodiode having a multiplier with alternating layers of one or more quantum wells and one or more spacers. A method of making the avalanche photodiode includes growing the multiplier on a substrate.

Abstract: A method for forming a semiconductor device comprising forming a stack of nanowires, the stack including a first nanowire having a first length, and a second nanowire having a second length, the second nanowire arranged above the first nanowire, forming a sacrificial gate stack on the stack of nanowires, growing a source/drain region on the first, second nanowires, removing the sacrificial gate stack to expose channel regions of the first and second nanowires, and forming a gate stack over the channel regions.

Abstract: A light emitting device includes a light emitting element, a terminal substrate and a fixing member. The light emitting element is a semiconductor laminate having a first semiconductor layer, a light emitting layer, and a second semiconductor layer that are laminated in that order, a first electrode connected to the first semiconductor layer, and a second electrode connected to the second semiconductor layer. The terminal substrate includes a pair of terminals connected to the first electrode and the second electrode, and an insulator layer that fixes the terminals. At least a part of the outer edges of the terminal substrate is disposed more to a center of the light emitting device than the outer edges of the semiconductor laminate. The fixing member fixes the light emitting element and the terminal substrate.

Abstract: A semiconductor device includes a substrate, a stacked structure on the substrate, and a vertical structure in a hole passing through the stacked structure. The stacked structure includes units stacked on top of each other in a direction perpendicular to a top surface of the substrate. The units include first units and second units between the first units. Each of the first units includes a first interlayer insulating layer on a first gate, and each of the second units includes a second interlayer insulating layer on a second gate. A ratio of a thickness of the second interlayer insulating layer with respect to a thickness of the second gate is different from a ratio of a thickness of the first interlayer insulating layer with respect to a thickness of the first gate.

Abstract: A method of bonding a plurality of die having first and second metal layers on a die surface to a board, comprising placing a first die onto a board comprising one of a ceramic or substrate board or metal lead frame having a solderable surface and placing the first die and the board into a reflow oven. The method includes reflowing at a first reflow temperature for a first period until the first metal board layer and at least one of the first and second metal die layers of the first die form an alloy to adhere the first die to the board. The alloy has a melting temperature higher than the first reflow temperature. Accordingly, additional die may be added at a later time and reflowed to attach to the board without causing the bonding of the first die to the board to fail.

Abstract: A pixel array substrate includes a first substrate, pixel units, data lines, scan lines, constant voltage lines, a constant voltage source, a constant voltage pad, and a conductive pattern. The first substrate has pixel regions and a peripheral region surrounding the pixel regions. The conductive pattern includes conductive lines interlaced with each other to form a net and a conductive frame that surrounds and is electrically coupled to the conductive lines. The conductive frame is in electrical contact with the constant voltage pad within the peripheral region. Each pixel region is defined by two adjacent scan lines and two adjacent data lines. A portion of one of the constant voltage lines located completely within each of the pixel regions is in electrical contact with one of the conductive lines within the pixel region. An OLED display including the pixel array substrate and another OLED are also provided.

Abstract: A semiconductor structure includes a first III-V compound layer. A second III-V compound layer is over the first III-V compound layer and is different from the first III-V compound layer in composition. A carrier channel is located at an interface of the first III-V compound layer and the second III-V compound layer. Slanted field plates are in an opening in a dielectric layer over the second III-V compound layer; the gate electrode is disposed in the opening.

Abstract: A light-emitting device includes a semiconductor layered structure; a conductive substrate disposed below the semiconductor layered structure; one or more upper electrodes, each disposed on a portion of an upper surface of the semiconductor layered structure; a lower electrode disposed on a lower surface of the semiconductor layered structure in a region spaced apart from regions of the lower surface of the semiconductor layered structure directly under the upper electrodes, the lower electrode being electrically connected between the semiconductor layered structure and the substrate; and one or more conduction prevention portions, each disposed on the lower surface of the semiconductor layered structure in at least a region located between (i) a region directly under a respective one of the one or more upper electrodes and (ii) the region on which the lower electrode is disposed.

Abstract: Disclosed is a graphene transistor using graphene as a channel region and a logic device using the same. A doping metal layer is provided over a graphene channel of the graphene transistor. The doping metal layer has a work function higher or lower than that of the graphene. When the doping metal layer has a work function lower than that of the graphene, the graphene, which is below the doping metal layer, is doped with an n-type. Also, when the doping metal layer has a work function higher than that of the graphene, the graphene, which is below the doping metal layer, is doped with a p-type. As described above, various aspects of junction may be implemented in the graphene channel, and three states may be obtained from a single transistor.

Abstract: According to one embodiment, a semiconductor device includes an insulating substrate including a pixel area and a peripheral circuit area around the pixel area, a first insulating layer which is provided on the insulating substrate and includes at least nitrogen, a second insulating layer at least provided on the first insulating layer of the peripheral circuit area, a first thin-film transistor which is provided above the first insulating layer of the pixel area and includes a first oxide semiconductor layer, and a second thin-film transistor which is provided on the second insulating layer of the peripheral circuit area and includes a second oxide semiconductor layer. The second insulating layer in the pixel area is thinner than that in the peripheral circuit area.

Abstract: A display unit includes a display panel and a first protective sheet. The display panel has a light-emitting surface. The first protective sheet is provided on the light-emitting surface. The first protective sheet provided in the display unit includes a first impact dispersion layer, a first strain relaxation layer, and a gel-like first impact absorption layer. The first impact dispersion layer has a pencil hardness of 3H or higher. The first strain relaxation layer has flexural strength and tensile strength both higher than the flexural strength and the tensile strength of the first impact dispersion layer. The gel-like first impact absorption layer has a thickness of a submillimeter order or more. The first impact absorption layer, the first strain relaxation layer, and the first impact dispersion layer are arranged in this order from the light-emitting surface.

Abstract: Semiconductor devices are provided. The semiconductor device includes a semiconductor layer having a first surface and a second surface that are opposite each other, a through electrode penetrating the semiconductor layer and having a protrusion that protrudes over the second surface of the semiconductor layer, a front-side bump disposed over the first surface of the semiconductor layer and electrically coupled to the through electrode, a polymer pattern disposed over the second surface of the semiconductor layer to enclose a part of the protrusion of the through electrode, and a back-side bump covering an upper surface and a sidewall of a remaining part of the protrusion of the through electrode and extending over a portion of the polymer pattern.

Abstract: A coated quantum dot and methods of making coated quantum dots are provided.

Abstract: A package substrate having an opening and through-substrate interconnect structures is attached to a temporary carrier such as an adhesive film. The active surface of an IC die is placed in contact with the carrier substrate within the opening, to temporarily attach the die to the carrier substrate. Another die is attached to the side of the first die furthest from the carrier substrate. In one embodiment, the dies are attached to each other using an epoxy so that their respective non-active surfaces face each other. Bond wires are connected between interconnects at the active surface of the second die and the substrate. The wires are then encapsulated. After removal of the carrier substrate, a build-up interconnect structure is formed that includes external interconnects of the package substrate, such as solder balls of a ball grid array package.