Abstract: The present invention relates to a display device including a static electricity discharge circuit. The display device according to an exemplary embodiment of the present invention includes: a thin film transistor array panel including a display area including a plurality of pixels and a peripheral area around the display area; a signal wire positioned at the peripheral area; and a static electricity discharge circuit unit positioned at the peripheral area and connected to the signal wire, wherein the static electricity discharge circuit unit includes a first portion and a second portion positioned at a same layer as a portion of the signal wire and facing each other with a separation space therebetween, and a connecting member positioned at a different layer from the first portion and the second portion and electrically connecting the first portion and the second portion.

Abstract: A highly reliable semiconductor device which uses an oxide semiconductor and in which a change in the electrical characteristics is suppressed is provided. The semiconductor device includes an island-shaped semiconductor layer over a base insulating layer, a pair of electrodes over the semiconductor layer, a barrier layer in contact with undersurfaces of the electrodes, a gate electrode over the semiconductor layer, and a gate insulating layer between the semiconductor layer and the gate electrode. The semiconductor layer contains an oxide semiconductor. The base insulating layer contains silicon oxide or silicon oxynitride. The electrodes each contain Al, Cr, Cu, Ta, Ti, Mo, or W. The barrier layer contains oxide containing one or more metal elements contained in the oxide semiconductor. Furthermore, the electrodes and the barrier layer extend to the outside of the semiconductor layer when seen from above.

Abstract: An organic light emitting device and a display device is provided. The organic light emitting device includes an anode, a cathode, and a light emitting layer disposed between the anode and the cathode; an electron transport layer disposed between the cathode and the light emitting layer, and the material of the electron transport layer is an organic metal chelate.

Abstract: A flexible display device including a substrate; a driving element layer including a plurality of thin film transistors on the substrate; a display element layer including organic light-emitting diodes electrically connected to the thin film transistors on the driving element layer; a light transmissive layer on the display element layer and configured to adjust a neutral plane of the flexible display device to lie at the driving element layer and the display element layer when the flexible display device is bent; and a back plate film attached to a back side of the substrate and having a cut portion formed in a center region where the flexible display device is bent.

Abstract: A method of forming a memory cell material comprises forming a first portion of a dielectric material over a substrate by atomic layer deposition. Discrete conductive particles are formed on the first portion of the dielectric material by atomic layer deposition. A second portion of the dielectric material is formed on and between the discrete conductive particles by atomic layer deposition. A memory cell material, a method of forming a semiconductor device structure, and a semiconductor device structure are also described.

Abstract: A non-volatile memory device and a manufacturing method thereof are provided. The memory device includes a substrate, a lower cell dielectric layer with gate conductors and a body unit conductor disposed on the lower cell dielectric layer and gates. Memory element conductors are disposed on the body unit and lower cell dielectric layer. An upper cell dielectric layer may be on the substrate and over the lower cell dielectric layer, body unit conductor and memory element conductors. The upper cell dielectric layer isolates the memory element conductors.

Abstract: Disclosed is a thin-film transistor substrate including: a substrate; a thin-film transistor formed on the substrate and including an active layer, a gate electrode, a source electrode, and a drain electrode; an identification (ID) mark formed on the substrate; and a metal layer contacting an upper surface of the ID mark.

Abstract: A memory device includes a plurality of stacks of conductive strips alternating with insulating strips. At least one of the insulating strips includes an insulating material with a dielectric constant equal to or lower than 3.6. A plurality of structures of a conductive material is arranged orthogonally over the stacks. Memory elements are disposed in interface regions at cross-points between side surfaces of the stacks and structures. The insulating strips can have equivalent oxide thicknesses EOT substantially greater than their respective physical thicknesses. The EOT can be at least 10% greater than the respective physical thicknesses. The at least one of the insulating strips can consist essentially of the insulating material with a dielectric constant equal to or lower than 3.6.

Abstract: One or more semiconductor arrangements are provided. The semiconductor arrangements include a buried layer over a well, a dielectric layer over the buried layer, a first gate stack over the dielectric layer and a S/D region disposed proximate the first gate stack. The S/D region has a first tip proximity region that extends under the first gate stack. One or more methods of forming a semiconductor arrangement are also provided. The methods include forming a S/D recess in at least one of a dielectric layer, a buried layer or a well, wherein the S/D recess is proximate a first gate stack and has a first recess tip proximity region that extends under the first gate stack as a function of the buried layer, and forming a S/D region in the S/D recess such that the S/D region has a first tip proximity region that extends under the first gate stack.

Abstract: A DC-to-DC converter includes: a substrate having a switching element region defined by an isolation layer; a transistor formed over the switching element region; a landing plate formed over the isolation layer; a capacitor formed over the landing plate and includes a bottom plate, a dielectric layer and a top plate; multi-layer metal lines disposed in an upper portion of the transistor and coupled with the transistor; and an interconnection portion coupled with the multi-layer metal lines to electrically connect the transistor with the capacitor.

Abstract: In a non-volatile memory in which writing/erasing is performed by changing a total charge amount by injecting electrons and holes into a silicon nitride film serving as a charge accumulation layer, in order to realize a high efficiency of a hole injection from a gate electrode, the gate electrode of a memory cell comprises a laminated structure made of a plurality of polysilicon films with different impurity concentrations, for example, a two-layered structure comprising a p-type polysilicon film with a low impurity concentration and a p?-type polysilicon film with a high impurity concentration deposited thereon.

Abstract: A transparent conductive thin film and an electronic device including the same are disclosed, the transparent conductive thin film including a titanium nitride or a zirconium nitride having a heterometal element selected from zinc (Zn), gallium (Ga), indium (In), and a combination thereof.

Abstract: A thin film transistor (TFT) and a method of driving the same are disclosed. The TFT includes: an active layer; a bottom gate electrode disposed below the active layer to drive a first region of the active layer; and a top gate electrode disposed on the active layer to drive a second region of the active layer. The TFT controls the conductivity of the active layer by using the bottom gate electrode and the top gate electrode.

Abstract: A semiconductor multi-layer substrate includes a substrate made of Si and a multi-layer semiconductor layer. The multi-layer semiconductor layer includes an active layer made of a nitride semiconductor, a first warp control layer being formed between the substrate and the active layer and giving a predetermined warp to the substrate, and a second warp control layer made of a nitride semiconductor of which amount of an increase in a warp per a unit thickness is smaller than an amount of increase in the warp per a unit thickness of the first warp control layer. A total thickness of the multi-layer semiconductor layer is equal to or larger than 4 ?m.

Abstract: GaN based nanowires are used to grow high quality, discreet base elements with c-plane top surface for fabrication of various semiconductor devices, such as diodes and transistors for power electronics.

Abstract: The disclosure provides a photo-detection device for use in long-wave infrared detection and a method of fabrication. The device comprises a GaSb substrate, a photo absorbing layer comprising InAs/InAsSb superlattice type-II, a barrier layer comprising AlAsSb, and a contact layer comprising InAs/InAsSb superlattice type-II. The barrier layer is configured to allow minority carrier holes current flow while blocking majority carrier electrons current flow between the photo-absorbing and contact layers. The disclosure further provides a method of producing the photo-detector using photolithography which includes selective etching of the contact layer that stops on the top of the barrier so no etching is made to the barrier layer so the barrier may operate as a passivator too. The disclosure presents an x-ray and photoluminescence results for InAs/InAsSb superlattice type-II material.

Abstract: The invention relates to a method for producing an electrical terminal support for an optoelectronic semiconductor body, comprising the following steps: providing a carrier assembly (1), which comprises a carrier body (11), an intermediate layer (12) arranged on an outer surface (111) of the carrier body (11), and a use layer (13) arranged on the intermediate layer (12); introducing at least two openings (4), which are mutually spaced in the lateral direction (L), in the use layer (13) via an outer surface (131) of the use layer (13), wherein the openings extend completely through the use layer (13) in the vertical direction (V); electrically insulating lateral surfaces (41) of the openings (4) and of the outer face (131) of the use layer (13); arranging electrically conductive material (6) at least in the openings (4), wherein after completion of the terminal carrier (100), the electrically conductive material (6) has an interruption (U) in the progression thereof along the outer surface (131) of the use lay

Abstract: A silicon nitride cap on a gate stack is removed by etching with a fluorohydrocarbon-containing plasma subsequent to formation of source/drain regions without causing unacceptable damage to the gate stack or source/drain regions. A fluorohydrocarbon-containing polymer protection layer is selectively deposited on the regions that are not to be etched during the removal of the nitride cap. The ability to remove the silicon nitride material using gas chemistry, causing formation of a volatile etch product and protection layer, enables reduction of the ion energy to the etching threshold.

Abstract: Methods for fabricating integrated circuits having improved active regions are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate having an upper surface and including active regions and isolation regions formed in a low voltage device area and in a high voltage device area. The method includes selectively forming voids between the isolation regions and the active regions in the high voltage device area to expose active side surfaces. The method further includes oxidizing the upper surface and the active side surfaces to form a gate oxide layer over the low voltage device area and the high voltage device area.

Abstract: Integrated circuits and fabrication methods are provided. The integrated circuit includes: a varying gate structure disposed over a substrate structure, the varying gate structure including a first gate stack in a first region of the substrate structure, and a second gate stack in a second region of the substrate structure; a first field-effect transistor in the first region, the first field-effect transistor including the first gate stack and having a first threshold voltage; and a second field-effect transistor in the second region, the second field-effect transistor including the second gate stack and having a second threshold voltage, where the first threshold voltage is different from the second threshold voltage. The methods include providing the varying gate structure, the providing including: sizing layer(s) of the varying gate structure with different thickness(es) in different region(s).