Abstract: Memristors, including memristors comprising a Schottky barrier, and related systems and methods are generally described.

Abstract: The invention provides a contact plug structure. The contact plug structure comprises a substrate and a dielectric layer, and a first contact hole located in the dielectric layer and penetrating into the substrate, the first contact hole has a first through hole portion located in the dielectric layer and a first groove located in the substrate, and the first through hole portion is communicated with the first groove, the maximum width of the first groove is larger than that of the first through hole portion in the direction parallel to the substrate surface. A barrier layer at least partially covering the sidewall of the first groove. A conductive pad layer is located on the bottom surface of the first groove. The conductive core layer is arranged on the conductive pad layer, and the barrier layer wraps the conductive pad layer and the conductive core layer.

Abstract: A memory device includes a substrate, word line layers, insulating layers, and memory cells. The word line layers are stacked above the substrate. The insulating layers are stacked above the substrate respectively alternating with the word line layers. The memory cells are distributed along a stacking direction of the word line layers and the insulating layers perpendicularly to a major surface of the substrate. Each memory cell includes a source line electrode and a bit line electrode, a first oxide semiconductor layer, and a second oxide semiconductor layer. The first oxide semiconductor layer is peripherally surrounded by one of the word line layers, the source line electrode, and the bit line electrode. The second oxide semiconductor layer is disposed between the one of the word line layers and the first oxide semiconductor layer.

Abstract: The present disclosure, in some embodiments, relates to a multi-dimensional integrated chip structure. The multi-dimensional integrated chip structure includes a first substrate having a first upper surface and a second upper surface above the first upper surface. A first outermost perimeter of the first upper surface is larger than a second outermost perimeter of the second upper surface. A second substrate is over the first substrate. The second substrate has a third upper surface above the second upper surface. A third outermost perimeter of the third upper surface is smaller than the second outermost perimeter of the second upper surface.

Abstract: A three-dimensional optoelectronic device package is disclosed. The three-dimensional optoelectronic device package comprises a first board having at least one surface on which a plurality of optoelectronic devices is disposed, and a second board having at least one surface on which a plurality of optoelectronic devices is disposed. A side of the second board is attached to the surface of the first board on which a plurality of optoelectronic devices is disposed to form an angle between the surface of the first board on which a plurality of optoelectronic devices is disposed and the surface of the second board on which a plurality of optoelectronic devices is disposed. A method for manufacturing a three-dimensional optoelectronic device package is also disclosed.

Abstract: A substrate has a front side including an electrical circuit and a rear side including an exposed zone that faces the electrical circuit. In an electrochemical treatment step, an electrical potential is laterally applied at least to the exposed zone of the rear side of the substrate, while the exposed zone is in contact with a chemically reactive substance. The electrical potential causes a lateral flow of electrical current at least in the exposed zone of the substrate. The lateral flow of current and the chemically reactive substance alter the substrate in at least the exposed zone.

Abstract: To provide a solid-state imaging element capable of further improving reliability. Provided is a solid-state imaging element including at least a first photoelectric conversion section, and a semiconductor substrate in which a second photoelectric conversion section is formed, in this order from a light incidence side, in which the first photoelectric conversion section includes at least a first electrode, a photoelectric conversion layer, a first oxide semiconductor layer, a second oxide semiconductor layer, and a second electrode in this order, and a film density of the first oxide semiconductor layer is higher than a film density of the second oxide semiconductor layer.

Abstract: A method of manufacturing a semiconductor device includes forming a plurality of work function metal layers and an oxygen absorbing layer over a channel region of the semiconductor device, including forming a first work function metal layer over the channel region, forming an oxygen absorbing layer over the first work function metal layer, forming a second work function metal layer over the oxygen absorbing layer. A gate electrode metal layer is formed over the plurality of work function metal layers. The work function metal layers, oxygen absorbing layer, and gate electrode metal layer are made of different materials.

Abstract: Disclosed are a flexible display panel, a flexible display device and a deformation detection method thereof, used for detecting deformation of the flexible display panel. The flexible display panel provided by embodiments of the present disclosure includes a flexible substrate, a display device and a piezoelectric sensor arranged in a stacked mode. The piezoelectric sensor includes a first electrode, a second electrode, and a piezoelectric layer positioned between the first electrode and the second electrode; the piezoelectric sensor is configured to generate an electrical signal under the action of stress produced by bending the flexible display panel; and a signal processing chip in the flexible display device is configured to determine deformation parameters of the flexible display panel according to the electrical signal.

Abstract: The present disclosure provides a display panel and a display device. A through-hole is defined in a bending area of the display panel, and after the bending area is bent along a bending center line, the through-hole forms a light transmitting area, and the light transmitting area is disposed on a light path of an electronic component. Based on the light transmitting area formed after bending the through-hole, the electronic component can be disposed under the display panel, thereby achieving a narrow frame design.

Abstract: The present disclosure relates to a neuron behavior-imitating electronic synapse device and a method of fabricating the same. According to one embodiment, the neuron behavior-imitating synapse device includes a first electrode having a lithium-doped surface, an active layer formed on the first electrode and including a polyelectrolyte and one or more metal nanoparticles, and a second electrode formed on the active layer.

Abstract: A semiconductor device includes a landing pad on a substrate, a lower electrode on the landing pad and connected to the landing pad, the lower electrode including an outer portion, the outer portion including first and second regions, and an inner portion inside the outer portion, a dielectric film on the lower electrode to extend along the first region of the outer portion, and an upper electrode on the dielectric film, wherein the outer portion of the lower electrode includes a metal dopant, a concentration of the metal dopant in the first region of the outer portion being different from a concentration of the metal dopant in the second region of the outer portion.

Abstract: According to an embodiment, a method of manufacturing an organic electronic device including a stack including a first electrode layer, one or more functional layers, and a second electrode layer, the one or more functional layers and the second electrode layer being formed in this order on the first electrode layer, comprises: a first layer forming step of forming a first layer 24 among the layers included in the stack; and a second layer forming step of forming a second layer on the first layer by using a coating solution containing a material for the second layer and a solvent with boiling point of 160° C. or more, the second layer being in contact with the first layer. In the first layer forming step, the first layer is formed with a thickness t smaller than a desired thickness such that the first layer has the desired thickness T due to an increase in a thickness of the first layer as the second layer is formed.

Abstract: The object of the present invention is to make it possible to form an LTPS TFT and an oxide semiconductor TFT on the same substrate. A display device includes a substrate having a display region in which pixels are formed. The pixel includes a first TFT using an oxide semiconductor 109. An oxide film 110 as an insulating material is formed on the oxide semiconductor 109. A gate electrode 111 is formed on the oxide film 110. A first electrode 115 is connected to a drain of the first. TFT via a first through hole formed in the oxide film 110. A second electrode 116 is connected to a source of the first TFT via a second through hole formed in the oxide film 110.

Abstract: An element includes an electron transportation layer containing nanoparticles, a QD layer containing QD phosphor particles, and a mixed layer sandwiched between the electron transportation layer and the QD layer to be adjacent to these layers. The mixed layer contains QD phosphor particles and nanoparticles.

Abstract: A method of three-dimensionally integrating elements such as singulated die or wafers and an integrated structure having connected elements such as singulated dies or wafers. Either or both of the die and wafer may have semiconductor devices formed therein. A first element having a first contact structure is bonded to a second element having a second contact structure. First and second contact structures can be exposed at bonding and electrically interconnected as a result of the bonding. A via may be etched and filled after bonding to expose and form an electrical interconnect to interconnected first and second contact structures and provide electrical access to this interconnect from a surface.

Abstract: A method for forming a semiconductor device. A substrate having a first region and a second region surrounding the first region is provided. The first region includes a first active area and a first gate. A dummy pattern is disposed on the substrate within the second region around a perimeter of the first region. A resist pattern masks the second region and includes an opening that exposes the first region. An ion implantation process is performed to implant dopants through the opening into the first active area not covered by the first gate within the first region, thereby forming doped regions in the first active area. A resist stripping process is performed to remove the resist pattern by using a sulfuric acid-hydrogen peroxide mixture (SPM) solution at a temperature that is higher than or equal to 120˜190 degrees Celsius. The substrate is subjected to a cleaning process.

Abstract: A piezo-resistor sensor includes a diffusion of a first conductivity type in a well of an opposite second type, contacts with islands in the diffusion, interconnects with the contacts, and a shield covers the diffusion between the contacts and extends over side walls of the diffusion between the contacts. Each interconnect covers the diffusion at the corresponding contact and extends over edges of the diffusion, and each island is at a side covered by its interconnect. A guard ring of the second type is around the diffusion. The shield covers the well between the diffusion and the ring and the edge of the ring facing the diffusion. If a gap between the shield and the interconnect is present, the ring bridges this gap, and/or the edges of the diffusion are completely covered by the combination of the shield and the interconnects.

Abstract: A method for forming a superjunction power semiconductor device includes forming multiple epitaxial layers of a first conductivity type on a semiconductor substrate and implanting dopants of a second conductivity type into each epitaxial layer to form a first group of implanted regions in a first region and a second group of implanted regions in a second region in each epitaxial layer. The multiple epitaxial layers are annealed to form multiple columns of the second conductivity type having slanted sidewalls across the first to last epitaxial layers. The columns include a first group of columns formed by the implanted regions of the first group and having a first grading and a second group of columns formed by the implanted regions of the second group and having a second grading, where the second grading is less than the first grading.

Abstract: A memory cell of a memory cell array includes a well region, a first doped region, a second doped region, a first gate structure, and a storage structure. The first doped region and the second doped region are formed in the well region. The first gate structure is formed over a first surface between the first doped region and the second doped region. The storage structure is formed over a second surface and the second surface is between the first surface and the second doped region. The storage structure is covered on a portion of the first gate structure, the second surface and an isolation structure.