Abstract: A semiconductor structure includes an interlayer dielectric layer, a first set of back-end-of-line interconnect structures disposed in the interlayer dielectric layer, and a second set of back-end-of-line interconnect structures at least partially disposed in the interlayer dielectric layer. Each of the first set of back-end-of-line interconnect structures has a first width and a first height providing a first aspect ratio. Each of the second set of back-end-of-line interconnect structures has a second width and a second height providing a second aspect ratio different than the first aspect ratio. The second width is greater than the first width, and the second height is different than the first height.

Abstract: A semiconductor device with integrated memory devices and metal-oxide-semiconductor (MOS) devices, including a substrate with a first area and a second area, multiple double-diffused metal-oxide-semiconductor (DMOS) devices on the first area, wherein the double-diffused metal-oxide-semiconductor (DMOS) device includes a field oxide on the substrate, a first gate dielectric layer adjacent to the field oxide, and a first polysilicon gate on the field oxide and the first gate dielectric layer, and multiple memory units on the second area, wherein the memory unit includes an oxide-nitride-oxide (ONO) tri-layer and a second polysilicon gate on the oxide-nitride-oxide (ONO) tri-layer, wherein a top surface of the second polysilicon gate of the memory unit in the second area and a top surface of the first polysilicon gate of the double-diffused metal-oxide-semiconductor (DMOS) in the first area are on the same level.

Abstract: A base substrate includes a supporting substrate comprising aluminum oxide, and a base crystal layer provided on a main face of the supporting substrate, comprising a crystal of a nitride of a group 13 element and having a crystal growth surface. At lease one of a metal of a group 13 element and a reaction product of a material of the supporting substrate and the crystal of the nitride of the group 13 element is present between the raised part and the supporting substrate. The reaction product contains at least aluminum and a group 13 element.

Abstract: This application discloses a pixel structure and a display device. The pixel structure includes a substrate unit, a first pixel unit, a second pixel unit, a scanning unit, a data unit, a switch unit, a shading unit and a plurality of electrode units. The first pixel unit, the second pixel unit, the scanning unit and the data unit are located on the substrate unit, respectively. The switch unit is electrically connected to the first pixel unit, the second pixel unit, the scanning unit and the data unit. The shading unit is located on the first pixel unit and the second pixel unit.

Abstract: Various embodiments of the present disclosure are directed towards a memory cell including a data storage structure disposed between a top electrode and a bottom electrode. The data storage structure includes a lower switching layer overlying the bottom electrode, and an upper switching layer overlying the lower switching layer. The lower switching layer comprises a dielectric material doped with a first dopant.

Abstract: Disclosed herein are methods for reducing MOSFET trench sidewall surface roughness. In some embodiments, a method includes providing a device structure including a well formed in an epitaxial layer, forming a plurality of trenches through the well and the epitaxial layer, and implanting the device structure to form a treated layer along a sidewall of just an upper portion of the device structure within each of the plurality of trenches. The method may further include etching the device structure to remove the treated layer.

Abstract: In an imaging element, a plurality of pixels each having a photoelectric conversion part is arranged in a two-dimensional matrix. Some of the plurality of pixels each have a polarizer placed therein on a side of a light beam incidence plane. At least some of pixels having no polarizer placed therein each have a material layer placed therein that prevents transmission of a light beam having a wavelength of a predetermined range, to reduce color mixture in the pixel having the polarizer placed therein.

Abstract: A semiconductor device has transistor portions and diode portions. The transistor portions have a semiconductor substrate of a first conductivity type, a first semiconductor region of a second conductivity type, second semiconductor regions of the first conductivity type, gate insulating films, gate electrodes, a first semiconductor layer of the first conductivity type, a third semiconductor region of the second conductivity type, a first electrode, and a second electrode. The diode portions have the semiconductor substrate, the first semiconductor region, the first semiconductor layer, a fourth semiconductor region of the first conductivity type, the first electrode, and the second electrode. A first depth of the first semiconductor layer from the back surface of the semiconductor substrate in the transistor portions is greater than a second depth of the first semiconductor layer from the back surface of the semiconductor substrate in the diode portions.

Abstract: A finFET device and a method of forming are provided. The device includes a transistor comprising a gate electrode and a first source/drain region next to the gate electrode, the gate electrode being disposed over a first substrate. The device also includes a first dielectric layer extending along the first source/drain region, and a second dielectric layer overlying the first dielectric layer. The device also includes a contact disposed in the first dielectric layer and in the second dielectric layer, the contact contacting the gate electrode and the first source/drain region. A first portion of the first dielectric layer extends between the contact and the gate electrode. The contact extends along a sidewall of the first portion of the first dielectric layer and a first surface of the first portion of the first dielectric layer, the first surface of the first portion being farthest from the first substrate.

Abstract: A device includes a vertical transistor comprising a first gate in a first trench, wherein the first gate comprises a dielectric layer and a gate region over the dielectric layer, and a second gate in a second trench, a high voltage lateral transistor immediately adjacent to the vertical transistor and a low voltage lateral transistor, wherein the high voltage lateral transistor is between the vertical transistor and the low voltage lateral transistor.

Abstract: An antifuse One-Time-Programmable memory cell includes a substrate, and a hybrid select transistor and a hybrid antifuse capacitor formed on the substrate. The hybrid select transistor includes a first gate dielectric layer formed on the substrate, wherein the first gate dielectric layer is thinner than 40 nm, a first high-voltage junction formed in the substrate, and a low-voltage junction formed in the substrate. The hybrid antifuse capacitor includes a second gate dielectric layer, wherein the second gate dielectric layer is thinner than 40 nm, which enables a low-voltage antifuse capacitor device, a second gate formed on the gate dielectric layer, a second high-voltage junction formed in the substrate, and a third high-voltage junction formed in the substrate.

Abstract: A method for producing a metal-insulator-metal (MIM) type structure is provided, including producing, on a first substrate, first and second separation layers arranged one against the other; producing, on the second separation layer, an insulator layer including a perovskite structure material; producing a first gold and/or copper layer on the insulator layer, forming at least one part of a first electrode; making the first gold and/or copper layer integral with a second substrate; and forming a mechanical separation at an interface between the first and the second separation layers, the first separation layer remaining integral with the first substrate and the second separation layer remaining integral with the insulator layer, the insulator layer being arranged between the first electrode and a second electrode including at least one metal layer.

Abstract: The present invention discloses a two-dimensional AlN material and its preparation method and application, wherein the preparation method comprises the following steps: (1) selecting a substrate and its crystal orientation; (2) cleaning the surface of the substrate; (3) transferring a graphene layer to the substrate layer; (4) annealing the substrate; (5) using the MOCVD process to introduce H2 to open the graphene layer and passivate the surface of the substrate; and (6) using the MOCVD process to grow a two-dimensional AlN layer. The preparation method of the present invention has the advantages that the process is simple, time saving and efficient. Besides, the two-dimensional AlN material prepared by the present invention can be widely used in HEMT devices, deep ultraviolet detectors or deep ultraviolet LEDs, and other fields.

Abstract: Embodiments disclosed herein include an electronics package and methods of forming such electronics packages. In an embodiment, the electronics package comprises a plurality of build-up layers. In an embodiment, the build-up layers comprise conductive traces and vias. In an embodiment, the electronics package further comprises a capacitor embedded in the plurality of build-up layers. In an embodiment, the capacitor comprises: a first electrode, a high-k dielectric layer over portions of the first electrode, and a second electrode over portions of the high-k dielectric layer.

Abstract: Systems, apparatuses, and methods related to semiconductor structure formation are described. An example apparatus includes a structural material for a semiconductor device. The structural material includes an orthosilicate derived oligomer having a number of oxygen (O) atoms each chemically bonded to one of a corresponding number of silicon (Si) atoms and a chemical bond formed between an element from group 13 of a periodic table of elements (e.g., B, Al, Ga, In, and Tl) and the number of O atoms of the orthosilicate derived oligomer. The chemical bond crosslinks chains of the orthosilicate derived oligomer to increase mechanical strength of the structural material, relative to the structural material formed without the chemical bond to crosslink the chains, among other benefits described herein.

Abstract: The present disclosure provides a display substrate and a display device. The display substrate comprises a base, a plurality of display units arranged on the base, a signal line and a control unit, wherein the signal line is configured to connect adjacent two display units of the plurality of display units; at least a part of the signal line is made of a shape memory material, and the part is deformed to different degrees under different excitation conditions; the control unit is configured to detect deformation of the base and apply a corresponding excitation condition to the signal line according to the deformation of the base, so that the signal line is in a deformation state adaptive to the deformation of the base.

Abstract: The present invention provides a display screen and a display device, and the display screen includes at least one first display region and a second display region located outside the at least one first display region; the at least one first display region includes a substrate disposed in the at least one first display region and a light-shielding layer disposed on the substrate; wherein, the light-shielding layer includes at least one first opening located in a non-pixel region between neighboring pixels, and external light enters the display screen through the at least one first opening.

Abstract: The embodiments of the present disclosure provide an array substrate and a method for manufacturing the same, and a display device. The array substrate includes a substrate, wherein the substrate has a display region and a peripheral region surrounding the display region, the display region has a plurality of pixels arranged in an array, and each of the plurality of pixels includes a light transmission region and a light shielding region, and a light shielding block covering at least a part of the light transmission region of at least one pixel close to the peripheral region of the plurality of pixels.

Abstract: The present disclosure provides an array substrate and a method of preparing the same. The array substrate includes a substrate, a gate, a gate insulation layer, an active layer, a crystallization layer, an oxide layer, a source/drain metal layer, and a passivation layer. After the crystallization layer is prepared, a mask plate is not removed and is used to protect an upper surface of the crystallization layer from oxidation reaction. Then, an oxide layer is formed on sidewalls of the crystallization layer and the active layer. The oxide layer is used to obstruct the source/drain metal layer from contacting the active layer. The source/drain metal layer is only in contact with the crystallization layer, thereby reducing a path of leakage current and achieving a purpose of reducing the leakage current.

Abstract: A method of forming a memory device that includes forming a first polysilicon layer using a first polysilicon deposition over a semiconductor substrate, forming an insulation spacer on the first polysilicon layer, and removing some of the first polysilicon layer to leave a first polysilicon block under the insulation spacer. A source region is formed in the substrate adjacent a first side surface of the first polysilicon block. A second polysilicon layer is formed using a second polysilicon deposition. The second polysilicon layer is partially removed to leave a second polysilicon block over the substrate and adjacent to a second side surface of the first polysilicon block. A third polysilicon layer is formed using a third polysilicon deposition. The third polysilicon layer is partially removed to leave a third polysilicon block over the source region. A drain region is formed in the substrate adjacent to the second polysilicon block.