Abstract: A memory device and method of forming the same are provided. The memory device includes a first memory cell disposed over a substrate. The first memory cell includes a transistor and a data storage structure coupled to the transistor. The transistor includes a gate pillar structure, a channel layer laterally wrapping around the gate pillar structure, a source electrode surrounding the channel layer, and a drain electrode surrounding the channel layer. The drain electrode is separated from the source electrode a dielectric layer therebetween. The data storage structure includes a data storage layer surrounding the channel layer and sandwiched between a first electrode and a second electrode. The drain electrode of the transistor and the first electrode of the data storage structure share a common conductive layer.

Abstract: The present disclosure provides an integrated circuit (IC) structure. The IC structure includes a semiconductor substrate; an interconnection structure formed on the semiconductor substrate; and a redistribution layer (RDL) metallic feature formed on the interconnection structure. The RDL metallic feature further includes a barrier layer disposed on the interconnection structure; a diffusion layer disposed on the barrier layer, wherein the diffusion layer includes metal and oxygen; and a metallic layer disposed on the diffusion layer.

Abstract: In an acoustic wave device, an antenna end resonator that is electrically closest to a first terminal is a first acoustic wave resonator. In each of the first acoustic wave resonator and a second acoustic wave resonator, a thickness of a piezoelectric layer is about 3.5? or less when a wavelength of an acoustic wave is denoted as ?. The first acoustic wave resonator and the second acoustic wave resonator satisfy at least one of a first condition, a second condition, and a third condition. The first condition is a condition that the first acoustic wave resonator further includes a dielectric film provided between the piezoelectric layer and an interdigital transducer electrode, and the second acoustic wave resonator does not include the dielectric film.

Abstract: Various methods and systems are provided for a multi-frequency transducer array. In one example, the transducer array may be fabricated via a wafer scale approach, where a first comb structure, with a first type of element, is formed by dicing a first acoustic stack and a second comb structure, with a second type of element, is formed by dicing a second acoustic stack. Combining the first and second comb structures may form a multi-frequency transducer array.

Abstract: A photoelectric conversion device includes: a substrate; a first photoelectric conversion element including a first substrate electrode, a first photoelectric conversion layer, and a first counter electrode; a second photoelectric conversion element including a second substrate electrode, a second photoelectric conversion layer, and a second counter electrode; and a connection including a groove, a conductive portion and a conductive layer, the conductive portion being provided in the groove and including a part of the first counter electrode, and the conductive portion and the conductive layer electrically connecting the first counter electrode and the second substrate electrode. The conductive layer overlaps the first counter electrode on an edge of the groove, and a total thickness of the conductive portion and the conductive layer is larger than a thickness of the first counter electrode.

Abstract: In the contact structure according to an exemplary aspect of the present disclosure and a display device including the same, the pixel may be designed regardless of the size of the contact hole by designing a size (or an area) of the contact hole to be larger than the contact area and applying different structures depending on the characteristics of the lower layer. Therefore, the size of the contact hole is increased so that the halftone mask may be easily applied and the number of masks may be advantageously reduced. Further, a degree of freedom of metal in the pixel design is increased so that the pixel may be designed in a high resolution model and the aperture ratio is increased without having the electrode margin.

Abstract: A method of manufacturing a semiconductor device including a substrate; a first nitride layer containing gallium on the substrate; and a second nitride layer containing silicon on the first nitride layer includes generating an etchant of a gas containing chlorine atoms or bromine atoms; and selectively removing the second nitride layer, wherein the etchant is generated by plasma discharge of the gas, wherein the second nitride layer and the first nitride layer are prevented from being irradiated with ultraviolet rays generated at a time of the plasma discharge, and wherein the selectively removing the second nitride layer includes etching the second nitride layer under a first atmosphere at a first pressure that is lower than a first saturated vapor pressure of a silicon compound and that is higher than a second saturated vapor pressure of a gallium compound.

Abstract: A semiconductor package includes a silicon substrate including a cavity and a plurality of through holes spaced apart from the cavity, a first semiconductor chip in the cavity, a plurality of conductive vias in the plurality of through holes, a first redistribution layer on the silicon substrate and connected to the first semiconductor chip and the conductive vias, and a second redistribution layer below the silicon substrate and connected to the first semiconductor chip and the plurality of conductive vias.

Abstract: A transistor is disclosed. The transistor includes a p-type region, an intrinsic region coupled to the p-type region, an n-type region coupled to the intrinsic region, and a gate electrode above the intrinsic region. The ferroelectric material is on a bottom, a first side and a second side of the gate electrode, and above the intrinsic region.

Abstract: Provided is an aluminum nitride film in which, aluminum nitride crystal grains containing a metal element differing from aluminum and substituting for aluminum are main crystal grains of a polycrystalline film formed of crystal grains, and a concentration of the metal element in a grain boundary between the aluminum nitride crystal grains in at least one region of first and second regions corresponding to both end portions of the polycrystalline film in a film thickness direction of the polycrystalline film is higher than a concentration of the metal element in a center region of the aluminum nitride crystal grain in the at least one region, and is higher than a concentration of the metal element in a grain boundary between the aluminum nitride crystal grains in a third region located between the first region and the second region in the film thickness direction of the polycrystalline film.

Abstract: A photoelectric conversion element for detecting the spot size of incident light, including a photoelectric conversion substrate provided with two main surfaces, and multiple first sensitivity sections and second sensitivity sections arranged in a prescribed direction. When sensitivity regions on the respective main surfaces of the multiple first sensitivity sections are defined as first sensitivity regions, and sensitivity regions that appear on the main surfaces of the second sensitivity sections are defined as second sensitivity regions, each of the first sensitivity regions receives at least a part of light incident on the main surfaces, and has a pattern in which, in accordance with enlargement of an irradiation region irradiated with incident light on the main surface, the proportion of the first sensitivity regions in the irradiation region with respect to the first sensitivity regions other than those in the irradiation region and the second sensitivity regions is decreased.

Abstract: Methods for forming image sensors that leverage cavity profiles and induced stresses. In some embodiments, the method includes forming a cavity in a substrate where the cavity has a cavity profile that is configured to accept a sensor pixel structure for an image sensor, forming at least one passivation layer in the cavity, and forming at least one optical layer in the cavity on at least a portion of one of the at least one passivation layer. The at least one optical layer is configured to provide, at least, pixel-to-pixel optical isolation of the sensor pixel structure. The method further includes forming the sensor pixel structure in the cavity on the at least one optical layer of the sensor pixel structure where the cavity profile is configured to control stress on the sensor pixel structure.

Abstract: A transistor heat dissipation module is adapted for at least one transistor. The transistor heat dissipation module includes a heat dissipation member and an elastic member. The heat dissipation member includes a first wall and a second wall opposite to each other and a first connecting member connected to the first wall and the second wall. An accommodating space is formed between the first wall and the second wall. The transistor is disposed in the accommodating space. The elastic member is disposed in the accommodating space and is located between the at least one transistor and the first wall to press the at least one transistor against the second wall. An assembly method of a transistor heat dissipation module is further provided.

Abstract: A nonvolatile memory device according to an embodiment includes a substrate, a gate electrode structure disposed on the substrate, a gate dielectric layer covering at least a portion of a sidewall surface of the gate electrode structure on the substrate, a channel layer and a resistance change structure that are sequentially disposed on the gate dielectric layer, and a plurality of bit line structures disposed inside the resistance change structure.

Abstract: The present invention discloses a method for creating spin-affected electric currents passively and feeding them into electric devices. The invention can be realized as either a rectangular black box incorporating coatings on top of and on the bottom of a conducting volume of material, or by coating a round-shaped wire or thread(s) of a cable. This is obtained by using a specific coating material on the conducting piece of material. The material may be piezoelectric, such as silicon dioxide (i.e. quartz) but also silicon carbide (SiC) may be used. Also, mixtures and composite arrangements are possible in order to create a coating. The manufactured add-on unit, when supplied with the input power or input signal, will act as an electron spin feeding device to the electric device because the electrons will be moving strongly within the interface area of the coating and the conducting material with aligned spins.

Abstract: A semiconductor device is provided. The semiconductor device includes a plurality of lower electrodes arranged on a semiconductor substrate in a honeycomb structure; and a support connected to the plurality of lower electrodes and defining a plurality of open areas through which the plurality of lower electrodes are exposed. A center point of each of the plurality of open areas is arranged at a center point of a triangle formed by center points of three corresponding neighboring lower electrodes among the plurality of lower electrodes.

Abstract: A photodetector is provided, including an active layer configured to generate charge carriers of a first type and of a second type by absorption of electromagnetic radiation; a first electrode configured to collect the charge carriers of the first type; and a second electrode configured to collect the charge carriers of the second type, the first electrode including a layer configured to collect the charge carriers of the first type, the layer including self-assembled monolayers, and nanowires comprising metal and functionalized by the self-assembled monolayers, the self-assembled monolayers of the layer are configured to functionalize the nanowires and to modify a work function of a material forming the nanowires. A method for manufacturing a photodetector and an electrode for a photodetector are also provided.

Abstract: A semiconductor module comprising a semiconductor apparatus and a cooling apparatus, where: the semiconductor apparatus includes a semiconductor chip and a circuit board on which the semiconductor chip is mounted; and the cooling apparatus includes: a top plate on which the semiconductor apparatus is mounted; a jacket including a side wall connected to the top plate, a bottom plate connected to the side wall and facing the top plate, and a cooling pin fin extending in such a manner as to taper from the bottom plate toward the top plate, where at least the bottom plate and the cooling pin fin are integrally formed, and at least one of ends of the cooling pin fin is firmly fixed to the top plate; and a coolant flow portion defined by the top plate and the jacket and for flow of coolant.

Abstract: A semiconductor apparatus comprises a first semiconductor region including a first surface and a second surface, in which a semiconductor of a first conductivity type is arranged, a second semiconductor region of the first conductivity type, which is arranged between the first surface and the second surface, a third semiconductor region of a second conductivity type, which is arranged in a region between the second semiconductor region and the second surface and on a side portion of the second semiconductor region, a fourth semiconductor region of the first conductivity type, which is arranged between the first surface and the second surface; and a fifth semiconductor region of the second conductivity type, which is arranged in a region between the fourth semiconductor region and the second surface and on a side portion of the fourth semiconductor region.

Abstract: A semiconductor device includes a cell array including a source structure, a peripheral circuit, an interconnection structure located between the cell array and the peripheral circuit and electrically coupled to the peripheral circuit, and a decoupling structure configured to prevent a coupling capacitor that occurs between the cell array and the interconnection structure.