Abstract: Embodiments herein describe techniques for a thin-film transistor (TFT) above a substrate. The transistor includes a gate electrode above the substrate, and a channel layer above the substrate, separated from the gate electrode by a gate dielectric layer. The transistor further includes a contact electrode above the channel layer and in contact with a contact area of the channel layer. The contact area has a thickness determined based on a Schottky barrier height of a Schottky barrier formed at an interface between the contact electrode and the contact area, a doping concentration of the contact area, and a contact resistance at the interface between the contact electrode and the contact area. Other embodiments may be described and/or claimed.

Abstract: The present disclosure provides a non-volatile flash memory device and a manufacturing method thereof. The non-volatile flash memory device comprises at least a plurality of memory cells in a memory area. The manufacturing method comprises: providing a substrate, and defining the memory area of the non-volatile flash memory device on the substrate; forming a plurality of stack gates of the plurality of memory cells on a substrate corresponding to the memory area, and the top of each stack gate is a memory control gate of the memory cell; etching the memory control gates to reduce the height of the memory control gates with the fluid photoresist filled among the plurality of stack gates of the plurality of memory cells as a mask; and removing the fluid photoresist.

Abstract: The present invention provides a display panel and a display module. The display panel comprises at least two pixel units. Each pixel units comprises a substrate, a thin film transistor (TFT) disposed on the substrate, and a pixel electrode disposed on the thin film transistor. The thin film transistor and the pixel electrode disposed in the same pixel unit are insulated from each other. The thin film transistor disposed in the pixel unit is electrically connected to a pixel electrode disposed in another pixel unit, which is disposed parallel to the pixel unit.

Abstract: Some embodiments include a transistor having an active region containing semiconductor material. The semiconductor material includes at least one element selected from Group 13 of the periodic table in combination with at least one element selected from Group 16 of the periodic table. The active region has a first region, a third region offset from the first region, and a second region between the first and third regions. A gating structure is operatively adjacent to the second region. A first carrier-concentration-gradient is within the first region, and a second carrier-concentration-gradient is within the third region. Some embodiments include methods of forming integrated assemblies.

Abstract: A field effect transistor includes a substrate and spacers over the substrate. The field effect transistor includes a channel recess cavity between the spacers, wherein a bottom-most surface of the channel recess cavity is parallel to the substrate top surface. The field effect transistor includes a gate stack, wherein the gate stack includes a bottom portion in the channel recess cavity and a top portion outside the channel recess cavity, the gate stack further includes a gate dielectric layer extending from the channel recess cavity along sidewalls of each of the pair of spacers, and the gate dielectric layer directly contacts the substrate below substrate top surface. The field effect transistor includes a strained source/drain (S/D) below the substrate top surface, wherein the strained S/D extends below the gate stack. The field effect transistor further includes a source/drain (S/D) extension substantially conformably surrounding the strained S/D.

Abstract: A display panel and a display device are provided. The display panel includes a substrate layer, a light emitting layer, a package layer, a filter layer and an organic flat layer. The organic flat layer covers the filter layer. The light emitting layer further includes a pixel area and a pixel interval area. The filter layer further includes an R/G/B filter area and a layer stacked area. The layer stacked area is a stacked structure of R/G/B three-layer filter layers. The layer stacked structure can thin the thickness of the display panel and improve the flexibility of the display panel.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to electronic fuse (e-fuse) cells integrated with a bipolar device and methods of manufacture. The structure includes: a bipolar device comprising a collector region, a base region and an emitter region; and an e-fuse integrated with and extending from the emitter region of the bipolar device.

Abstract: An embodiment of the present application provides a preparation method of a mask assembly, including: fixing, after stretching and aligning a blocking, the blocking on a side of a frame; opening at least one stretching align hole and at least one evaporation align mark in the fixed blocking and frame; fixing, after stretching and aligning a mask sheet, the mask sheet on a side of the blocking away from the frame according to the stretching align hole; and opening at least one evaporation align mark in the fixed mask sheet to obtain the mask assembly.

Abstract: A display device is disclosed, wherein the display device includes a light emitting unit, including: a first semiconductor layer; an active layer disposed on the first semiconductor layer; a second semiconductor layer disposed on the active layer; and a protecting layer disposed on the second semiconductor layer, wherein the protecting layer has a region in which oxygen atomic percentages decrease toward the second semiconductor layer.

Abstract: A porous region structure and a method of fabrication thereof are disclosed. The porous region structure is characterized by having a hard mask interface region with non-uniform pores sealed and thereby excluded functionally from the structure. The sealing of the hard mask interface region is done using a hard mask deposited on top of an anodization hard mask used to define the porous region of the structure. By excluding the hard mask interface region, the porosity ratio and the equivalent specific surface of the porous region structure can be controlled or quantified with higher accuracy. Corrosion due to exposure of an underlying metal layer of the structure is also significantly reduced by sealing the hard mask interface region.

Abstract: An illustrative device disclosed herein includes a first memory cell comprising a first memory gate positioned above an upper surface of a semiconductor substrate and a second memory cell comprising a second memory gate positioned above the upper surface of the semiconductor substrate. In this example, the device also includes a conductive word line structure positioned above the upper surface of the semiconductor substrate between the first and second memory gates, wherein the conductive word line structure is shared by the first and second memory cells.

Abstract: A micro-LED display panel including a substrate, an anisotropic conductive film, and a plurality of micro-LEDs is provided. The anisotropic conductive film is disposed on the substrate. The micro-LEDs and the anisotropic conductive film are disposed at the same side of the substrate, and the micro-LEDs are electrically connected to the substrate through the anisotropic conductive film. Each of the micro-LEDs includes an epitaxial layer and an electrode layer electrically connected to the epitaxial layer, and the electrode layers comprises a first electrode and a second electrode which are located between the substrate and the corresponding epitaxial layer. A ratio of a thickness of each of the electrode layers to a thickness of the corresponding epitaxial layer ranges from 0.1 to 0.5, and a gap between the first electrode and the second electrode of each of the micro-LEDs is in a range of 1 ?m to 30 ?m.

Abstract: A method includes forming a first-type deep well with a first impurity of a first conductivity type in a semiconductor substrate; doping a second impurity of a second conductivity type into the first-type deep well to form a second-type doped region, in which a concentration of the first impurity in the first-type deep well is greater than a concentration of the second impurity in the second-type doped region and less than about ten times the concentration of the second impurity in the second-type doped region; forming a field oxide partially embedded in the semiconductor substrate, the field oxide laterally extending from a first side of the second-type doped region; forming a second-type well of the second conductivity type in the first-type deep well and on a second side of the second-type doped region opposite the first side of the second-type doped region.

Abstract: Provided is an opto-electronic device having low dark noise and a high signal-to-noise ratio. The opto-electronic device may include: a first semiconductor layer doped to have a first conductivity type; a second semiconductor layer disposed on an upper surface of the first semiconductor layer and doped to have a second conductivity type electrically opposite to the first conductivity type; a transparent matrix layer disposed on an upper surface of the second semiconductor layer; a plurality of quantum dots arranged to be in contact with the transparent matrix layer; and a first electrode provided on a first side of the transparent matrix layer and a second electrode provided on a second side of the transparent matrix layer opposite to the first side, wherein the first electrode and the second electrode are electrically connected to the second semiconductor layer.

Abstract: The present invention relates to a method for manufacturing a nonvolatile memory, including the steps of: forming a gate oxide layer on a substrate; forming a stacked capacitor of a storage cell after making a logic gate polysilicon undertake at least two deposition processes; and removing the extra logic gate polysilicon by an etching process to form a storage transistor and a peripheral logic transistor. According to the method of the present invention, the stacked capacitor of the storage transistor is formed by depositing at least twice, and the memory is manufactured in a standard logic process, which makes the manufacturing process of the memory simpler, the memory has good compatibility with the logic process and has low cost.

Abstract: A method for depositing a phosphorus doped silicon arsenide film is disclosed. The method may include, providing a substrate within a reaction chamber, heating the substrate to a deposition temperature, exposing the substrate to a silicon precursor, an arsenic precursor, and a phosphorus dopant precursor, and depositing the phosphorus doped silicon arsenide film over a surface of the substrate. Semiconductor device structures including a phosphorus doped silicon arsenide film deposited by the methods of the disclosure are also provided.

Abstract: A feedback 1T DRAM device that has a partial insulating film structure is provided. A body region may be divided into two or more in a channel direction by pn junctions and/or partial insulating layers, and gates may be formed on each of the divided body regions. The present invention can be operated by filling and subtracting electrons in the energy well of the conduction band and holes in the energy well of the valence band, respectively. In addition, it is possible to maximize retention time and improve operation reliability by reducing carrier loss by energy barriers of pn junctions and/or partial insulating layers.

Abstract: A memory device includes a substrate having an upper surface; a stacked structure disposed on the upper surface of the substrate, wherein the stacked structure includes a first insulating layer, a first conductive layer, a second insulating layer; a second conductive layer and a third insulating layer sequentially stacked on the substrate; a plurality of channel structures penetrating the stacked structure and electrically connected to the substrate, wherein each of the channel structures includes an upper portion corresponding to the second conductive layer and a lower portion corresponding to the first conductive layer; a memory layer disposed between the second conductive layer and the upper portion; and a plurality of isolation structures penetrating the stacked structure to separate the stacked structure into a plurality of sub-stacks.

Abstract: A display module is provided. The display module includes: a substrate; a thin film transistor (TFT) layer formed on one surface of the substrate; and a plurality of micro LEDs disposed on the TFT layer. The plurality of micro LEDs are transferred from a transfer substrate to the TFT layer by a laser beam radiated to the transfer substrate through openings of a mask. The openings correspond to regions in which the respective micro LEDs of the transfer substrate are arranged and the openings correspond to a width, a length, or a unit area of each of the micro LEDs.

Abstract: The present application discloses a thin-film transistor (TFT) array substrate and a display panel. The TFT array substrate includes an active layer and a source/drain electrode disposed on the active layer. The active layer includes an electrode coverage region, a channel region, and a first peripheral region disposed around the electrode coverage region and the channel region. The active layer located in the first peripheral region is distributed in multi-sections.