Abstract: There are provided a DDR controller, a method for implementing the same and a chip, which are applicable to the field of DDR controller technology. The method includes the steps of: parsing a plurality of buffered commands concurrently (S501); prejudging relationships between a bank and a row of an address to be accessed by each parsed command and a bank and a row of an address for a currently executed command; and transmitting a PRECHARGE command and an ACTIVE command in advance. With the above technical solution, the PRECHARGE command and ACTIVE command which should have been transmitted serially can be transmitted in advance by being hidden in parallel in a Read or WRITE period to thereby make full use of a bandwidth of a DDR device.

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for hybrid checkpointed memory. A method includes referencing data of a range of virtual memory of a host. The referenced data is already stored by a non-volatile medium. A method includes writing, to a non-volatile medium, data of a range of virtual memory that is not stored by the non-volatile medium. A method includes providing access to data of a range of virtual memory from a non-volatile medium using a persistent identifier associated with referenced data and written data.

Abstract: A method for dynamically balancing the allocation of data among a plurality of physical data storage devices having a plurality of RAID devices defined thereon, wherein at least one of the plurality of RAID devices is comprised of at least one of a different type of physical storage device or a different number of physical data storage devices than at least one other of the plurality of RAID devices, includes determining a usage factor unique to each RAID device and balancing data I/O based at least in part on the usage factor.

Abstract: A method, computer program product, and computing system for receiving an indication of a cold cache event within a storage system. The storage system includes a multi-tiered data array including at least a faster data tier and a slower data tier. A data list that identifies at least a portion of the data included within the faster data tier of the multi-tiered data array is obtained from the multi-tiered data array. At least a portion of the data identified within the data list is requested from the multi-tiered data array, thus defining the requested data. The requested data is received from the multi-tiered data array.

Abstract: Embodiments are directed to a method of accessing a data frame, wherein a first portion of the data frame is in a first memory block, and wherein a second portion of the data frame is in a second memory block. The method includes determining that an access of the data frame crosses a boundary between the first second memory blocks, determining that an attempted translation of an address of the first portion of the data frame in the first memory block did not result in a translation fault, and accessing the first portion of the data frame. The method further includes, based at least in part on a determination that an attempted translation of an address of the second portion of the data frame in the second memory block resulted in a translation fault, accessing at least one default character as a replacement for accessing the second portion of the data frame.

Abstract: A buffer cache interposed between a non-volatile memory and a host may be partitioned into segments that may operate with different policies. Cache policies include write-through, write and read-look-ahead. Write-through and write back policies may improve speed. Read-look-ahead cache allows more efficient use of the bus between the buffer cache and non-volatile memory. A session command allows data to be maintained in volatile memory by guaranteeing against power loss.

Abstract: A data processing system includes a host processor and a graphics processing unit operable to process data under the control of an operating system executing on the host processor. The graphics processing unit can be switched between a normal mode of operation in which the it has read and write access to data that is stored in non-protected memory regions 9 but no or write-only access to any protected memory regions 8, and a protected mode of operation in which it has read and write access to data that is stored in protected memory regions 8 but only has read-only access to any non-protected memory regions 9. The data processing system further comprises a mechanism for switching the graphics processing unit from its normal mode of operation to the protected mode of operation, and from its protected mode of operation to the normal mode of operation.

Abstract: A method, computer program product, and computing system for storing a plurality of frontend data chunks within a cache system. The plurality of frontend data chunks correspond to a plurality of backend data chunks stored within a data array. A device weight is determined for each of the plurality of backend data chunks. The device weight is indicative of the type of storage device upon which each of the plurality of backend data chunks is stored within the data array. A deletion score is assigned to each of the plurality of frontend data chunks. Each deletion score is based, at least in part, upon the device weight determined for its corresponding backend data chunk.

Abstract: A method of securely erasing a non-volatile semiconductor mass memory has a plurality of physical memory units assigned either to a first memory area which can be addressed via an interface of the semiconductor mass memory or to a second memory area which cannot be addressed via the interface, and a controller that changes assignment of the memory units to the first memory area and to the second memory area according to an algorithm that produces wear leveling upon receiving a command to overwrite memory units assigned to the first memory area via the interface.

Abstract: An example method of providing deduplication support for remote direct memory access (RDMA) memory includes detecting that a first memory page and a second memory page are identical. A first mapping maps a first virtual memory address (VMA) to a first physical memory address (PMA) of the first memory page. A second mapping maps a second VMA to a second PMA of the second memory page. An RDMA memory region includes the first memory page. The method also includes updating the first mapping to map from the first VMA to the second PMA. The method further includes re-registering the RDMA memory region for RDMA.

Abstract: A system for data management in a computing storage environment includes a processor device, operable in the computing storage environment, that divides a plurality of counters tracking write and discard storage operations through Non Volatile Storage (NVS) space into first, accurate, and second, fuzzy, groups where the first, accurate, group is one of updated on a per operation basis, while the second, fuzzy, group is one of updated on a more infrequent basis as compared to the first, accurate group.

Abstract: Techniques are described for processing signal information from a high speed communication bus. The techniques include determining spatial regions on an eye by sampling a plurality of time and voltage points to determine a two-dimensional matrix. Then, the points are assigned a numerical value from combined time and voltage functions based upon a distance from eye edges (e.g., minimum setup time requirement and minimum hold time requirement along the time dimension). Sampling to generate the matrix may comprise selecting an initial point, splitting a first margin along a first dimension into equally spaced regions, and then sampling a second margin along a second dimension into equally spaced regions. Determining the points is based on shifting a strobe signal (DQS) position and a data signal (DQ) position and running a plurality of memory built-in self test (BIST) engines and a plurality of results of BIST tests.

Abstract: Embodiments relate to cache coherency verification using ordered lists. An aspect includes maintaining a plurality of ordered lists, each ordered list corresponding to a respective thread that is executed by a processor, wherein each ordered list comprises a plurality of atoms, each atom corresponding to a respective operation performed in a cache by the respective thread that corresponds to the ordered list in which the atom is located, wherein the plurality of atoms in an ordered list are ordered based on program order. Another aspect includes determining a state of an atom in an ordered list of the plurality of ordered lists. Another aspect includes comparing the state of the atom in an ordered list to a state of an operation corresponding to the atom in the cache. Yet another aspect includes, based on the comparing, determining that there is a coherency violation in the cache.

Abstract: Embodiments relate to cache coherency verification using ordered lists. An aspect includes maintaining a plurality of ordered lists, each ordered list corresponding to a respective thread that is executed by a processor, wherein each ordered list comprises a plurality of atoms, each atom corresponding to a respective operation performed in a cache by the respective thread that corresponds to the ordered list in which the atom is located, wherein the plurality of atoms in an ordered list are ordered based on program order. Another aspect includes determining a state of an atom in an ordered list of the plurality of ordered lists. Another aspect includes comparing the state of the atom in an ordered list to a state of an operation corresponding to the atom in the cache. Yet another aspect includes, based on the comparing, determining that there is a coherency violation in the cache.

Abstract: A processing unit includes a first storage entity being updated at a first clock cycle (CLK1) for holding a master copy of processing unit state. The processing unit further includes at least two shadow storage entities being updated with update information of the first storage entity. A shadow storage entity running at a second clock cycle (CLK2) is slower than the first clock cycle (CLK1). The first storage entity is coupled with the shadow storage entities via an intermediate storage entity, and the intermediate storage entity provides multiple storage stages for buffering consecutive update information of the first storage entity. Selection circuitry is adapted to provide one update information contained in one storage stage to the shadow storage entity with the active clock edge of the second clock cycle (CLK2) in order to update said shadow storage entity.

Abstract: Memory performance in a computer system that implements large page mappings is improved by dynamically tuning the page scan rate at which a memory sharing module (e.g., in a hypervisor) performs small page scanning operations that identify and exploit potential small page sharing opportunities within large pages. In operation, when free memory is relatively low, the hypervisor adjusts the page scan rate based on a statistical estimate of the percentage of virtual small pages that are mapped to physical large pages that are shareable. In this fashion the hypervisor dynamically tunes the sharing rate to reflect memory usage of applications. Further, unlike conventional approach to page sharing, the hypervisor proactively breaks large pages before resorting to more expensive memory reclamation techniques, such as ballooning and host swapping.

Abstract: Regardless of which of the multiple storage subsystems provided with the same identification information is accessed from a plurality of host computers, multiple volumes provided with the same identification information among the storage subsystems are subjected to extent exclusion sharing. Therefore, a multiplex volume provided with the same identification information among the plurality of storage subsystems and a first storage subsystem for processing input/output requests by the channel command to the multiplex volume are provided, wherein if the channel command received from the host computer or via a control unit of a second storage subsystem is an input/output request of the multiplex volume, a control unit of the first storage subsystem determines the access authority regarding an extent range of the multiplex volume designated by the channel command, based on information on whether an input/output processing regarding the extent range is already executed based on another request.

Abstract: A method and apparatus for virtual address mapping are provided. The method includes determining an offset value respective of at least a first portion of code stored on a code memory unit, generating a first virtual code respective of the first portion of code and a second virtual code respective of a second portion of code stored on the code memory unit; mapping the first virtual code to a first virtual code address and the second virtual code to a second virtual code address; generating a first virtual data respective of the first portion of data and a second virtual data respective of the second portion of data; and mapping the first virtual data to a first virtual data address and the second virtual data to a second virtual data address.

Abstract: Apparatus, computer readable medium, integrated circuit, and method of moving a plurality of data items to a first cache or a second cache are presented. The method includes receiving an indication that the first cache requested the plurality of data items. The method includes storing information indicating that the first cache requested the plurality of data items. The information may include an address for each of the plurality of data items. The method includes determining based at least on the stored information to move the plurality of data items to the second cache. The method includes moving the plurality of data items to the second cache. The method may include determining a time interval between receiving the indication that the first cache requested the plurality of data items and moving the plurality of data items to the second cache. A scratch pad memory is disclosed.

Abstract: Storage devices including a flash memory and a memory controller, and write memory block allocating methods of the storage devices are provided. A write memory block allocating method may include storing a pre-allocation table in a Random Access Memory (RAM) of a memory controller. The pre-allocation table may include allocation order information of a pre-allocated memory block included in a flash memory. The method may also include receiving a write request from a host, determining whether a write memory block for the write request can be allocated according to the pre-allocation table and allocating the pre-allocated memory block as the write memory block according to the pre-allocation table when the write memory block can be allocated according to the pre-allocation table.