Abstract: This invention describes an apparatus, computer architecture, memory structure, memory control, and cache memory operation method for multi-core processor. A logic core shares requests when faced with immediate cache memory units having low yield or deadly performance. The core mounts (multiple) cache unit(s) that might already be in use by other logic cores. Selected cache memory units serve multiple logic cores with the same contents. The shared cache memory unit(s) serves all the mounting cores with cache search, hit, miss, and write back functions. The method recovers a logic core whose cache memory block is not operational by sharing cache memory blocks which might already engage other logic cores. The method is used to improve reliability and performance of the remaining system.

Abstract: The described system provides that backend array-based snapshots may be created separately on each site of a cluster, and then the snapshots fixed so as to be consistent and/or otherwise identical among the plurality of sites. The system advantageously allows creation of a consistent cluster-wide snapshot with minimal or no I/O delays. In an embodiment, the system provides for use of a change tracker that tracks the metadata of all the I/Os incoming to the volumes being snapped. When the system wants to create a snapshot on all sites, the change tracker is activated on each site separately for the volumes being snapped. A snapshot is then created on each of the cluster sites/backend storage arrays separately. The change trackers are then ordered to stop tracking. A snapshot fixing procedure is then initiated.

Abstract: A translation system can translate a storage request having multiple fields to a physical address using the fields as keys to traverse a map. By using a map table, multiple storage services can be condensed into a single map traversal. The map can be made of nodes that include one or more node entries. The node entries can be stored in a hashed storage area or sorted storage area of a node. A node entry of root nodes or inner nodes can include a link to a next node. A node entry of a leaf node can include a physical address. Using the request fields as a key to a node, a node entry can be determined. A pointer in a root node entry or inner node entry can be followed to a next node. A physical address in a leaf node can be the translation of the storage request.

Abstract: A method of training chip select for a memory module. The method includes programming a memory controller into a mode wherein a command signal is active for a programmable time period. The method then programs a programmable delay line of the chip select with a delay value and performs initialization of the memory module. A read command is then sent to the memory module to toggle a state of the chip select. A number of data strobe signals sent by the memory module in response to the read command are counted. A determination is made whether the memory module is in a pass state or an error state based on a result of the counting.

Abstract: A first timing reference signal and a second timing reference signal are sent to a memory device. The second timing reference signal has approximately a quadrature phase relationship with respect to the first timing reference signal. A plurality of serial data patterns are received from the memory device. The transitions of the first timing reference and the second timing reference determining when transitions occur between the bits of the plurality of data patterns. Timing indicators associated with when received transitions occur between the bits of the plurality of data patterns are received from the memory device. The timing indicators are each measured using a single sampler. Based on the timing indicators, a first duty cycle adjustment for the first timing reference signal, a second duty cycle adjustment for the second timing reference signal, and a quadrature phase adjustment are determined and applied.

Abstract: A computer-implemented method includes receiving, utilizing a processor, a fencing command at a storage controller from an initiating host system. The fencing command identifies a shared volume. Additionally, the computer-implemented method includes determining which other host systems are connected to the shared volume, and fencing each of the other host systems connected to the shared volume by setting a fencing indicator for each of the other host systems. Still yet, the computer-implemented method includes sending a notification to each of the other host systems that have been fenced, and receiving an unfencing command from at least one of the other host systems that have been fenced.

Abstract: A method for updates in a storage system is provided. The method includes writing identifiers, associated with data to be stored, to storage units of the storage system and writing trim records indicative of identifiers that are allowed to not exist in the storage system to the storage units. The method includes determining whether stored data corresponding to records of identifiers is valid based on the records of the identifiers and the trim records.

Abstract: A data storage device comprises a non-volatile memory comprising a plurality of blocks, each configured to store a plurality of physical pages at predetermined physical locations. A controller programs and reads data stored in a plurality of logical pages. A volatile memory comprises a logical-to-physical address translation map configured to enabling determination of the physical location, within one or more physical pages, of the data stored in each logical page. A plurality of journals may be stored, each comprising a plurality of entries associating one or more physical pages to each logical page. At startup, the controller may read at least some of the plurality of journals in an order and rebuild the map; indicate a readiness to service data access commands after the map is rebuilt; rebuild a table from the map and, based thereon, select block(s) for garbage collection after having indicated the readiness to process the commands.

Abstract: A system includes: input-output devices including a first input-output device having a first input-output characteristic and a second input-output device having a second input-output characteristic, and a control device. The control device is configured to when jobs include a first job in which a ratio between reading and writing included in the first job is more suitable for the first input-output characteristic than the second input-output characteristic, a second job having a dependency relationship with the first job and in which a ratio between reading and writing included in the second job is more suitable for the second input-output characteristic than the first input-output characteristic, and a third job having a dependency relationship with neither the first job nor the second job, control submitting order of the jobs into nodes, coupling the input-output devices and the nodes, and copying of execution result data by the jobs between the input-output devices.

Abstract: A system and method for verifying cache coherency in a safety-critical avionics processing environment includes a multi-core processor (MCP) having multiple cores, each core having at least an L1 data cache. The MCP may include a shared L2 cache. The MCP may designate one core as primary and the remainder as secondary. The primary core and secondary cores create valid TLB mappings to a data page in system memory and lock L1 cache lines in their data caches. The primary core locks an L2 cache line in the shared cache and updates its locked L1 cache line. When notified of the update, the secondary cores check the test pattern received from the primary core with the updated test pattern in their own L1 cache lines. If the patterns match, the test passes; the MCP may continue the testing process by updating the primary and secondary statuses of each core.

Abstract: A virtual machine host server includes a virtual machine in which a guest operating system is installed and operated, a cache manager for processing at least one of an open request, a close request, and an input/output request for a disk image file of the virtual machine, which is stored in a storage system, and managing a boot workload map and a boot segment, a cache device for caching the boot segment, and a prefetch manager for prefetching the boot segment from the cache device.

Abstract: Implementations described and claimed herein provide systems and methods for allocating and managing resources for a deduplication table. In one implementation, an upper limit to an amount of memory allocated to a deduplication table is established. The deduplication table has one or more checksum entries, and each checksum entry is associates a checksum with unique data. A new checksum entry corresponding to new unique data is prevented from being added to the deduplication table where adding the new checksum entry will cause the deduplication table to exceed a size limit. The new unique data has a checksum that is different from the checksums in the one or more checksum entries in the deduplication table.

Abstract: Disclosed herein are system, method, and computer program product embodiments for accessing data of a memory. A method embodiment operates by receiving one or more requests for data stored across at least a first memory area and a second memory area of a memory. The method continues with performing, by at least one processor, a wrapped read of data within a first memory area of the memory. The method then performs, by the at least one processor, a continuous read of data within a second memory area of the memory, the second memory area being adjacent to the first memory area. The continuous read starts at a first boundary of the second memory area, and is performed automatically after the wrapped read of data within the first memory area.

Abstract: Systems, methods, and computer program products for providing operating system (O/S) redundancy in a computing system are provided. One system includes a host computing device, a plurality of memory devices, and a sub-loader coupled between the host computing device and the plurality of memory devices. Each memory device stores a respective O/S and the sub-loader is configured such that the plurality of memory devices appear transparent to the host computing device. One method includes designating, a first logical unit device as a primary logical unit device and subsequently determining that the first logical unit device is unresponsive. The designation is removed from the first logical unit device and a second logical unit device is designated as a new primary logical unit device. One computer program product includes instructions for performing the above method.

Abstract: According to one embodiment, a controller for a nonvolatile semiconductor memory that stores data expressed using n levels (n is a natural number not less than 3) page by page includes an extraction unit and a conversion unit. The extraction unit extracts a second data stream shorter than a first data stream from the first data stream that includes a plurality of data written to the nonvolatile semiconductor memory. The conversion unit converts the second data stream into a third data stream longer than the second data stream, when a difference between threshold voltages of the nonvolatile semiconductor memory corresponding to adjacent two data included in the second data stream is a first level difference. The third data stream has a second level difference smaller than the first level difference.

Abstract: This disclosure is related to media cache cleaning based on workload. In some examples, a read-modify-write (RMW) operation may merge new data with existing data and the merge may be interrupted without losing the amount of work already processed. This can be particularly useful for shingled magnetic recording (SMR) systems that utilize a large cache, such as a media cache, that can accumulate many entries that might need to be merged with existing data. An RMW operation can be interrupted such that a host command does not timeout.

Abstract: The present invention relates to methods and apparatuses for eliminating or mitigating the effects of the corruption of contents in an external flash memory, such as that which can occur during a power interruption. Embodiments of the invention include methods to log external flash memory program and erase operations redundantly to dedicated buffer partitions in the flash memory itself. The log information from external serial flash memory is used to erase the sector that was being programmed or erased when power was removed. According to certain aspects, the redundant storage of log information in embodiments ensures that if one version of the log information is corrupted, the other version can be used.

Abstract: Methods, apparatuses, systems, and devices are described for determining use of areas of a disk drive. In one method, a score of an area node of the disk drive may be increased each time the area node is accessed during a time interval of a series of time intervals. When each time interval elapses, each existing score of the area nodes (e.g., scores of area nodes that have non-zero scores) may be decreased. Further, after being decreased, each existing score may be saved. In such a manner, a time series analysis of data accesses may be implemented. The increases in score may account for the number of accesses during a given interval, and the decreases in score may account for time passage (e.g., time-weighting the scores). Thus, more frequent accesses and more recent accesses result in higher accumulated scores for the corresponding area nodes.

Abstract: According to one embodiment, a computer system includes a first memory unit, a second memory unit having a data transfer rate lower than that of the first memory unit and a controller. The controller controls transfer of unit data. The unit data includes an indicating portion indicating whether the unit data is to be retained in the second memory unit. When the unit data is transferred from the second memory unit to the first memory unit and the unit data is to be retained in the second memory unit, the controller sets a first state to the indicating portion of the respective unit data. When the unit data is transferred from the first memory unit to the second memory unit, the controller writes the respective unit data in which the indicating portion is set to the first state, to the second memory unit.

Abstract: A system may include a memory that includes a plurality of pages, a processor, and a translation lookaside buffer (TLB) that includes a plurality of entries. The processor may be configured to access data from a subset of the plurality of pages dependent upon a first virtual address. The TLB may be configured to compare the first virtual address to respective address information included in each entry of the plurality of entries. The TLB may be further configured to add a new entry to the plurality of entries in response to a determination that the first virtual address fails to match the respective address information included in each entry of the plurality of entries. The new entry may include address information corresponding to at least two pages of the subset of the plurality pages.