Abstract: Systems and methods for managing shared cache by multi-core processor. An example processing system comprises: a plurality of processing cores, each processing core communicatively coupled to a last level cache (LLC) slice; and a cache control logic coupled to the plurality of processing cores, the cache control logic configured to perform one of: making an LLC slice of an inactive processing core available to an active processing core or power gating the LLC slice, based on estimating cache requirements by active processing cores.

Abstract: A data writing method, a memory controller, and a memory storage device are provided. The method is applied to control a rewritable non-volatile memory module that includes two memory units. The method includes: configuring a plurality of logical addresses and mapping the logical addresses to at least parts of physical erasing units in the two memory units; receiving a writing command from a host system to instruct to write data into one of the logical addresses; writing the data into a physical erasing unit in the two memory units; determining one of the memory units where the physical erasing unit belongs to; if the physical erasing unit belongs to one of the memory units, erasing another physical erasing unit in the other memory unit while writing the data into the physical erasing unit. Accordingly, a speed of writing data into the memory storage device by the host system is accelerated.

Abstract: An apparatus configured to write, in a non-volatile memory, an address conversion table for wear leveling of the non-volatile memory includes a holding unit configured to hold a first address conversion table for wear leveling of a first block of the non-volatile memory, a second address conversion table for wear leveling of a second block other than the first block of the non-volatile memory, and a third address conversion table for wear leveling of a third block other than the first block of the non-volatile memory; and a writing unit configured to write, in the first block, a replication of the second address conversion table in addition to one replication of the first address conversion table and to write, in the third block, another replication of the first address conversion table in addition to a replication of the third address conversion table.

Abstract: An apparatus configured to write, in a non-volatile memory, an address conversion table for wear leveling of the non-volatile memory includes a holding unit configured to hold a first address conversion table for wear leveling of a first block of the non-volatile memory, a second address conversion table for wear leveling of a second block other than the first block of the non-volatile memory, and a third address conversion table for wear leveling of a third block other than the first block of the non-volatile memory; and a writing unit configured to write, in the first block, a replication of the second address conversion table in addition to one replication of the first address conversion table and to write, in the third block, another replication of the first address conversion table in addition to a replication of the third address conversion table.

Abstract: A system and method that allows idle process logic blocks in a memory device to be utilized when the idle process logic blocks would otherwise be remaining idle as the current memory commands are executed. Utilizing the otherwise idle process logic blocks in the memory device allows more optimized use of the process logic blocks while not slowing or otherwise interfering with the execution of the current memory commands. The otherwise idle process logic blocks can perform additional operations for subsequently fetched memory commands that may otherwise cause delays in execution of the subsequently fetched memory commands.

Abstract: Systems and methods for managing cache configurations are disclosed. In accordance with a method, a system management control module may receive access rights of a host to a logical storage unit and may also receive a desired caching policy for caching data associated with the logical storage unit and the host. The system management control module may determine an allowable caching policy indicator for the logical storage unit. The allowable caching policy indicator may indicate whether caching is permitted for data associated with input/output operations between the host and the logical storage unit. The system management control module may further set a caching policy for data associated with input/output operations between the host and the logical storage unit, based on at least one of the desired caching policy and the allowable caching policy indicator. The system management control module may also communicate the caching policy to the host.

Abstract: Embodiments of an invention for sharing memory in a secure processing environment are disclosed. In one embodiment, a processor includes an instruction unit and an execution unit. The instruction unit is to receive an instruction to match an offer to make a page in an enclave page cache shareable to a bid to make the page shareable. The execution unit is to execute the instruction. Execution of the instruction includes making the page shareable.

Abstract: A memory system includes: a non-volatile memory device; and a controller for checking operation information of a requested ISP operation, performing a first ISP operation when the requested ISP operation is not requested in the past, and performing a second ISP operation when the requested ISP operation is also requested in the past. During the first ISP operation, the controller may read out two or more requested data from the non-volatile memory device in response to the operation information of the requested ISP operation, generate resultant data by performing a predetermined operation to the read-out requested data, output the resultant data to a host, and store the resultant data in the non-volatile memory device. During the second ISP operation, the controller may read out the resultant data corresponding to the requested ISP operation from the non-volatile memory device, and output the read-out resultant data to the host.

Abstract: Embodiments are directed to a method of accessing a data frame, wherein a first portion of the data frame is in a first memory block, and wherein a second portion of the data frame is in a second memory block. The method includes determining that an access of the data frame crosses a boundary between the first second memory blocks, determining that an attempted translation of an address of the first portion of the data frame in the first memory block did not result in a translation fault, and accessing the first portion of the data frame. The method further includes, based at least in part on a determination that an attempted translation of an address of the second portion of the data frame in the second memory block resulted in a translation fault, accessing at least one default character as a replacement for accessing the second portion of the data frame.

Abstract: Methods for deciding whether to store data in a non-volatile memory (NVM) storage portion of a hybrid drive including the NVM storage portion and a disk storage portion are provided. One such method involves generating a queue for storing candidate addresses and a priority level for each of the candidate addresses, receiving a read command and a range of addresses for the disk storage portion, determining a relative distance between reads of a first address corresponding with a second address within the range of addresses, storing, when the relative distance is less than a relative distance threshold, a first candidate address, corresponding to the second address, and a respective priority level in the queue, and storing, when the priority level of the first candidate address is greater than a priority level threshold, data corresponding to the first candidate address in the NVM storage portion.

Abstract: The present disclosure includes apparatuses and methods for data compression and management. A number of methods include receiving a number of data segments corresponding to a managed unit amount of data, determining a respective compressibility of each of the number of data segments, compressing each of the number of data segments in accordance with its respective determined compressibility, forming a compressed managed unit that includes compressed and/or uncompressed data segments corresponding to the number of data segments corresponding to the managed unit amount of data, and forming a page of data that comprises at least the compressed managed unit.

Abstract: For a cache in which a plurality of frequently accessed data segments are temporarily stored, reference count information of the plurality of data segments, in conjunction with least recently used (LRU) information, is used to determine a length of time to retain the plurality of data segments in the cache according to a predetermined weight, where notwithstanding the LRU information, those of the plurality of data segments having a higher reference counts are retained longer than those having lower reference counts.

Abstract: For each access request received at a shared cache of the data processing device, a memory access pattern (MAP) monitor predicts which of the memory banks, and corresponding row buffers, would be accessed by the access request if the requesting thread were the only thread executing at the data processing device. By recording predicted accesses over time for a number of access requests, the MAP monitor develops a pattern of predicted memory accesses by executing threads. The pattern can be employed to assign resources at the shared cache, thereby managing memory more efficiently.

Abstract: Upon receipt of an I/O request instructing storage of data in a storage device 106 from a host apparatus, a storage apparatus 100 selects a de-duplication process method to be applied to the received data, based on at least any of influence on processing performance of the storage apparatus 100 to be performed by execution of a first de-duplication process method (inline method) in which the de-duplication process is performed on the data immediately after the receipt of the I/O request, influence on the processing performance of the storage apparatus 100 to be performed by execution of a second de-duplication process method (post-process method) in which the de-duplication process is performed on the data at later timing, and the size of a temporary storage device 106b to be required for the processing of the data by the second de-duplication process method.

Abstract: Embodiments are directed to a computer implemented method of accessing a data frame, wherein a first portion of the data frame is in a first memory block, and wherein a second portion of the data frame is in a second memory block. The method includes initiating, by a processor, an access of the data frame. The method further includes accessing, by the processor, the first portion of the data frame. The method further includes, based at least in part on a determination that the processor does not have access to the second memory block, accessing at least one default character as a replacement for accessing the second portion of the data frame.

Abstract: A mapping table H2F update technique for a FLASH memory is disclosed. In a disclosed data storage device, the controller updates a logical-to-physical address mapping table between a host and the FLASH memory in accordance with a group count of a buffer block of the FLASH memory. The group count reflects a logical address distribution of write data buffered in the buffer block and with non-updated logical-to-physical address mapping information. The higher the group count, the more dispersed the logical address distribution. In this manner, each update of the logical-to-physical address mapping table just takes a short time.

Abstract: Techniques are generally described for cache management in a processor with a cache. In response to receiving a bulk memory modification instruction, data blocks of the cache associated with the bulk memory modification instruction may be identified. A cache coherence state of the identified data blocks may also be identified. The updated cache coherence state may be indicative of a zero value of the data blocks and the cache coherence state of the identified data blocks may be updated without modification to a cache data array.

Abstract: A method to convert lock-free algorithm to wait-free using a hardware accelerator includes (i) executing a plurality of software threads by a plurality of processing units associated, the plurality of software threads is associated with at least one operation, (ii) generating at least one of a read request or a write request at the hardware accelerator based on the execution, (iii) generating at least one operation includes PARAM and read request or the write request at the hardware accelerator, (iv) checking, an operation specific condition of at least one software thread of the plurality of software threads, and (v) updating, at least one read value or write value and at least one state variable upon the operation specific condition being an operation success. The operation specific condition includes an operation success or an operation failure based on the PARAM, the read request, or the write request.

Abstract: There are provided a DDR controller, a method for implementing the same and a chip, which are applicable to the field of DDR controller technology. The method includes the steps of: parsing a plurality of buffered commands concurrently (S501); prejudging relationships between a bank and a row of an address to be accessed by each parsed command and a bank and a row of an address for a currently executed command; and transmitting a PRECHARGE command and an ACTIVE command in advance. With the above technical solution, the PRECHARGE command and ACTIVE command which should have been transmitted serially can be transmitted in advance by being hidden in parallel in a Read or WRITE period to thereby make full use of a bandwidth of a DDR device.

Abstract: Techniques for backup management are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for backup management comprising the steps of receiving power level information from a backup client, determining a factor, based at least in part on the power level information, affecting a backup time window for the backup client, identifying a portion of data of the backup client for backup based on the determination, and providing an instruction to the backup client communicating the identified portion of data.