Abstract: A lateral light-emitting diode backlight module includes a base, a circuit board, and at least a light emitting diode wherein the base having a heat conductor, the circuit board having a conductive pad formed on a surface thereof, and the circuit board disposed on the heat conductor and connected to the heat conductor. Each light emitting diode comprising a substrate, a heat sink fastened to the substrate and connected to the heat conductor, an LED chip disposed on the heat sink and emits light laterally, and a pin mounted on the substrate and extended to the conductive pad of the circuit board.

Abstract: A semiconductor wafer includes a plurality of chip areas, a scribe line area, a bonding pad, a probing pad, and a pad connection wiring. The plurality of chip areas are configured to be arranged in a matrix form. The scribe line area is configured to separate the plurality of chip areas from each other. The bonding pad is configured to be connected with an external terminal. The probing pad is configured to be contacted with a probe wire. The pad connection wiring is configured to electrically connect the bonding pad to the probing pad. The bonding pad and the probing pad are located at a predetermined distance from each other in each of the plurality of chip areas. The pad connection wiring has a portion located in the scribe line area.

Abstract: There is provided a semiconductor device 10 including a solder resist 16 for protecting a wiring pattern 14 electrically connected to a semiconductor chip 11 via an internal connection terminal 12, characterized in that the solder resist 16 is arranged to cover the upper surface of the portion of the wiring pattern 14 not corresponding to the arrangement region of the external connection terminal 17 and the side surface 14B of the wiring pattern 14 and that the area of the solder resist 16 assumed when the upper surface 13A of an insulation layer 13 is viewed from above is substantially the same as that of the wiring pattern 14 assumed when the upper surface 13A of the insulation layer 13 is viewed from above.

Abstract: A passivation film and a method of forming the same are provided, the passivation film being used in a plasma display panel etc. In the passivation film, a first MgO layer, an intervening layer, and a second MgO layer are laminated and a laser is then irradiated to oxidize the intervening layer. Simultaneously, defects are formed at the interfaces of the first and second MgO layers. Accordingly, a plasma discharge firing voltage greatly decreases, and the total power consumption of the plasma display panel is significantly reduced.

Abstract: A method for processing a substrate comprising at least a buried oxide (BOX) layer and a semiconductor material layer is provided. The method includes etching the semiconductor material layer to form a vertical semiconductor material structure overlying the BOX layer, leaving an exposed portion of the BOX layer. The method further includes exposing a top surface of the exposed portion of the BOX layer to an oxide etch resistant species to form a thin oxide etch resistant layer overlying the exposed portion of the BOX layer.

Abstract: A method of forming a vertical field effect transistor includes etching an opening into semiconductor material. Sidewalls and radially outermost portions of the opening base are lined with masking material. A semiconductive material pillar is epitaxially grown to within the opening adjacent the masking material from the semiconductor material at the opening base. At least some of the masking material is removed from the opening. A gate dielectric is formed radially about the pillar. Conductive gate material is formed radially about the gate dielectric. An upper portion of the pillar is formed to comprise one source/drain region of the vertical transistor. Semiconductive material of the pillar received below the upper portion is formed to comprise a channel region of the vertical transistor. Semiconductor material adjacent the opening is formed to comprise another source/drain region of the vertical transistor. Other aspects and implementations are contemplated.

Abstract: The present invention provides a semiconductor thin film which can be manufactured at a relatively low temperature even on a flexible resin substrate. As a semiconductor thin film having a low carrier concentration, a high Hall mobility and a large energy band gap, an amorphous film containing zinc oxide and tin oxide is formed to obtain a carrier density of 10+17 cm?3 or less, a Hall mobility of 2 cm2/V·sec or higher, and an energy band gap of 2.4 eV or more. Then, the amorphous film is oxidized to form a transparent semiconductor thin film 40.

Abstract: A semiconductor device includes a molding resin layer and a semiconductor element encapsulated with the molding resin layer. The molding resin layer has an opening. A surface of the semiconductor element is partially exposed outside the molding resin layer through the opening. A groove is located in the surface of the semiconductor element around the opening of the molding resin layer. The groove is filled with the molding resin layer to produce anchor effect that enhances adhesive force of the molding resin layer to the surface of the semiconductor element around the opening.

Abstract: A hetero semiconductor corner region, which is a current-concentration relief region that keeps a reverse bias current from concentrating on the convex corner, is arranged in a hetero semiconductor region. Thereby, a current concentration on the convex corner can be prevented. As a result, an interrupting performance can be improved at the time of interruption, and at the same time, the generation of the hot spot where in a specific portion is prevented at the time of conduction to suppress deterioration in a specific portion, thereby ensuring a long-term reliability.

Abstract: The present invention provides an organic thin film transistor and method for fabricating the same. The organic thin film transistor has a substrate and a gate electrode that is positioned on the substrate. A gate insulator has a stacked structure comprising an inorganic gate insulator and an organic gate insulator that are positioned on the gate electrode. An organic semiconductor layer is positioned on the gate insulator to overlap the gate electrode. Accordingly, an organic thin film transistor that has flexibility, decreased leakage current, and a low threshold is formed.

Abstract: A nanoscopic transistor is made by forming an oxide layer on a semiconductor substrate, applying resist, patterning the resist using imprint lithography to form a pattern aligned along a first direction, applying a first ion-masking material over the pattern, selectively lifting it off to leave a first ion mask to form a gate, forming doped regions by implanting a suitable dopant, applying another layer of resist and patterning the second resist layer using imprint lithography to form a second pattern aligned along a second direction, applying a second ion-masking material over the second pattern, selectively lifting it off to leave a second ion mask defined by the second pattern, and forming second doped regions in the substrate by implanting a suitable second dopant selectively in accordance with the second ion mask. The method may be used to make an array of nanoscopic transistors.

Abstract: A metal oxide semiconductor device comprising a substrate, at least an isolation structure, a deep N-type well, a P-type well, a gate, a plurality of N-type extension regions, an N-type drain region, an N-type source region and a P-type doped region is provided. The N-type extension regions are disposed in the substrate between the isolation structures and either side of the gate, while the N-type drain region and the N-type source region are respectively disposed in the N-type extension regions at both sides of the gate. The P-type well surrounds the N-type extension regions, and the P-type doped region is disposed in the P-type well of the substrate and is isolated from the N-type source region by the isolation structure.

Abstract: A metal gate thermocouple is provided. The thermocouple is configured to measure local temperatures of a device. The thermocouple is a passive device which senses temperature using the thermoelectric principle that when two dissimilar electrically conductive materials are joined, an electrical potential (voltage) is developed between the two materials. The voltage between the materials varies with the temperature of the junction (joint) between the materials. The thermocouple device includes a first conductor comprising a first material formed over a thin oxide layer or a shallow trench isolation (STI) structure and a second conductor comprising a second material formed over the thin oxide layer or the STI structure. The second conductor overlaps with the first conductor to form a thermocouple junction or dimension at least more than an alignment tolerance. The first and second materials are chosen such that the thermocouple junction formed between them exhibits a non-zero Seebeck coefficient.

Abstract: Methods of forming a microelectronic structure are described. Embodiments of those methods include forming a first plurality of openings through a first surface of a substrate, forming a p-type TFTEC material within the first plurality of openings, forming a second plurality of openings substantially adjacent to the first plurality of openings through the first surface of the substrate, and then forming an n-type TFTEC material within the second plurality of openings.

Abstract: A multi-chip stack module provides increased circuit density for a given surface chip footprint. The multi-chip stack module comprises support structures alternating with standard surface mount type chips to form a stack wherein the support structures electrically interconnect the chips. Various embodiments disclose a structure and method for interconnecting a plurality of generally planar chips in a vertical stack such that common signals are connected in the stack and individually-accessed signals are separated within the stack.

Abstract: Objects are to reduce damage to a semiconductor integrated circuit by external stress and to increase the manufacturing yield of a thinned semiconductor integrated circuit. A single crystal semiconductor layer separated from a single crystal semiconductor substrate is used for a semiconductor element included in the semiconductor integrated circuit. Moreover, a substrate which is formed into a thin shape and provided with the semiconductor integrated circuit is covered with a resin layer. In a separation step, a groove for separating a semiconductor element layer is formed in the supporting substrate, and a resin layer is provided over the supporting substrate in which the groove is formed. After that, the resin layer and the supporting substrate are cut in the groove so as to be divided into a plurality of semiconductor integrated circuits.

Abstract: A LDMOS with double LDD and trenched drain is disclosed. According to some preferred embodiment of the present invention, the structure contains a double LDD region, including a high energy implantation to form lightly doped region and a low energy implantation thereon to provide a low resistance path for current flow without degrading breakdown voltage. At the same time, a P+ junction made by source mask is provided underneath source region to avoid latch-up effect from happening.

Abstract: A power semiconductor device has a power field effect transistors connected in a bridge circuit (16), parallel circuit or series circuit (18), the power semiconductor device (30) having a base power semiconductor chip (1) with large-area external contacts (S1, D1) on the top side (31) and rear side (32) and carrying at least one stacked power semiconductor chip (2). The stacked power semiconductor chip (2) is surface-mounted with at least one large-area external electrode (D2) on a correspondingly large-area external electrode (S1) of the top side (31) of the base power semiconductor chip (1). At least one metallic structured spacer (33) is arranged between the surface-mounted external electrodes (S1, D2) of the base power semiconductor chip (1) and the stacked power semiconductor chip (2). The structure of the spacer (33) has at least one cutout (34) for a non-surface-mountable connecting element (35) of the base power semiconductor chip (1).

Abstract: Disclosed are embodiments of a wafer that incorporates fill structures with varying configurations to provide uniform reflectance. Uniform reflectance is achieved by distributing across the wafer fill structures having different semiconductor materials such that approximately the same ratio and density between the different semiconductor materials is achieved within each region and, optimally, each sub-region. Alternatively, it is achieved by distributing across the wafer fill structures, including one or more hybrid fill structure containing varying proportions of different semiconductor materials, such that approximately the same ratio between the different semiconductor materials is achieved within each region and, optimally, each sub-region.

Abstract: An exemplary light emitting diode includes a substrate, a LED chip, a first heat conductor, and a second heat conductor. The substrate comprises a first surface and an opposite second surface. The LED chip is positioned on the first surface of the substrate and it has a first electrode and a second electrode. The first heat conductor is attached to the second surface of the substrate and electrically connected to the first electrode of the LED chip. The second heat conductor is extending through the first heat conductor and insulated from the second heat conductor, and electrically connected to the second electrode of the LED chip.