Abstract: A diode includes an anode of a first conductivity type; a first cathode of the first conductivity type; and a second cathode of a second conductivity type opposite the first conductivity type. A lightly-doped region of the first conductivity type is under and vertically overlaps the anode and the first and the second cathodes. The portion of the lightly-doped region directly under the second cathode is fully depleted at a state when no bias voltage is applied between the anode and the second cathode.

Abstract: Methods and systems for forming multigate devices and systems are disclosed. In accordance with one such method, a fin is formed on a semiconductor substrate including a carbon-doped semiconductor layer. Further, a first portion of semiconductor material that is beneath the fin is removed to form a void beneath the fin by etching the material such that the fin is supported by at least one supporting pillar of the semiconducting material and such that the carbon-doped semiconductor layer prevents the etching from removing at least a portion of the fin. A dielectric material is deposited in the void to isolate the fin from a second portion of semiconductor material that is below the void. In addition, source and drain regions are formed in the fin and a gate structure is formed over the fin to fabricate the multigate device such that the dielectric material reduces current leakage beneath the device.

Abstract: According to one embodiment, a semiconductor device includes a first insulating film formed above a substrate, wires formed on the first insulating film, an air gap formed between the adjacent wires, and a second insulating film formed on the wires and the air gap. Each of the wires has a metal film formed on the first insulating film and a hard mask formed on the metal film, the hard mask has a first layer and a second layer, a second internal angle formed by the under surface and the side surface of the second layer on a cross section of the second layer is smaller than a first internal angle formed by the under surface and the side surface of the first layer on a cross section of the first layer, and the top surface of the air gap is higher than the top surface of the metal film.

Abstract: There is such an issue with a TFT using an oxide semiconductor film that oxygen deficit is generated in a surface region of the oxide semiconductor film after performing plasma etching of a source-drain electrode, and the off-current becomes increased. Disclosed is the TFT which includes: a gate electrode on an insulating substrate as a substrate; a gate insulating film on the gate electrode; an oxide semiconductor film on the gate insulating film; and a source/drain electrode on the oxide semiconductor film. It is the characteristic of the TFT that a surface layer containing at least either fluorine or chlorine exists in a part of the oxide semiconductor film where the source/drain electrode is not superimposed.

Abstract: A biometric sensor panel includes (a) a first flexible substrate, (b) a plurality of first electrodes formed on the first flexible substrate, the first electrodes being arranged in a first direction, (c) a semiconductor layer formed on the first electrodes, (d) a second flexible substrate, (e) a plurality of second electrodes formed on the second flexible substrate, the second electrodes being arranged in a second direction crossing the first direction, and (f) a pressure sensitive conductive layer formed on the second electrodes, wherein the first and second flexible substrates face each other such that the semiconductor layer is in contact with the pressure sensitive conductive layer.

Abstract: A fabricating method of an array substrate includes forming source and drain electrodes in each of pixel regions on a substrate; forming an organic semiconductor layer and a gate insulating layer on the source and drain electrodes, the organic semiconductor layer having an island shape and contacting facing ends of the source and drain electrodes, the gate insulating layer having a same plane shape as the organic semiconductor layer; forming a first passivation layer on the gate insulating layer; forming a gate electrode on the first passivation layer in the pixel region, the gate electrode corresponding to the gate insulating layer; forming a second passivation layer on the gate electrode, the second passivation layer having a drain contact hole exposing the drain electrode; and forming a pixel electrode on the second passivation layer, the pixel electrode contacting the drain electrode through the drain contact hole.

Abstract: A light emitting device according to one embodiment includes a light emitting element that emits light having a wavelength of 380 nm to 470 nm; a CASN first red phosphor that is disposed on the light emitting element; a sialon second red phosphor that is disposed on the light emitting element; and a sialon green phosphor that is disposed on the light emitting element.

Abstract: Voltage programmable anti-fuse structures and methods are provided that include at least one conductive material island atop a dielectric surface that is located between two adjacent conductive features. In one embodiment, the anti-fuse structure includes a dielectric material having at least two adjacent conductive features embedded therein. At least one conductive material island is located on an upper surface of the dielectric material that is located between the at least two adjacent conductive features. A dielectric capping layer is located on exposed surfaces of the dielectric material, the at least one conductive material island and the at least two adjacent conductive features. When the anti-fuse structure is in a programmed state, a dielectric breakdown path is present in the dielectric material that is located beneath the at least one conductive material island which conducts electrical current to electrically couple the two adjacent conductive features.

Abstract: A method of manufacturing an array substrate for a fringe field switching mode liquid crystal display includes: forming an auxiliary insulating layer having a first thickness; forming first and second photoresist patterns on the auxiliary insulating layer; performing an ashing to remove the second photoresist pattern and expose the auxiliary insulating layer therebelow; performing a dry etching to remove the auxiliary insulating layer not covered by the first photoresist pattern and expose a first passivation layer and to form an insulating pattern below the first photoresist pattern, the insulating pattern and the first photoresist pattern forming an undercut shape; forming a transparent conductive material layer having a fourth thickness less than the first thickness; and performing a lift-off process to remove the first photoresist pattern and the transparent conductive material layer thereon together and form a pixel electrode.

Abstract: A thin film transistor capable of stably obtaining good performance is provided. The thin film transistor includes an organic semiconductor layer, and a protective layer and a source electrode and a drain electrode formed on the organic semiconductor layer. The protective layer is disposed at least in a region between the source electrode and the drain electrode.

Abstract: A semiconductor device includes a semiconductor substrate; gates, spacers on both sides of the respective gates, and source and gain regions on both sides of the respective spacers, which are formed on the semiconductor substrate; lower contacts located on the respective source and gain regions and abutting outer-sidewalls of the spacers, with bottoms covering at least a portion of the respective source and gain regions; an inter-layer dielectric layer formed on the gates, the spacers, the source and gain regions, and the lower contacts, wherein the respective source and gain regions of each of the transistor structures are isolated from each other by the inter-layer dielectric layer; and upper contacts formed in the inter-layer dielectric layer and corresponding to the lower contacts. Methods for fabricating such a semiconductor device and for manufacturing contacts for semiconductor devices.

Abstract: Group III nitride semiconductor crystals of a size appropriate for semiconductor devices and methods for manufacturing the same, Group III nitride semiconductor devices and methods for manufacturing the same, and light-emitting appliances. A method of manufacturing a Group III nitride semiconductor crystal includes a process of growing at least one Group III nitride semiconductor crystal substrate on a starting substrate, a process of growing at least one Group III nitride semiconductor crystal layer on the Group III nitride semiconductor crystal substrate, and a process of separating a Group III nitride semiconductor crystal, constituted by the Group III nitride semiconductor crystal substrate and the Group III nitride semiconductor crystal layer, from the starting substrate, and is characterized in that the Group III nitride semiconductor crystal is 10 ?m or more but 600 ?m or less in thickness, and is 0.2 mm or more but 50 mm or less in width.

Abstract: A plurality of wires and electrodes are formed by forming a first conductive film, selectively forming a resist over the first conductive film, forming a second conductive film over the first conductive film and the resist, removing the second conductive film formed over the resist by removing the resist, forming a third conductive film so as to cover the second conductive film formed over the first conductive film, and selectively etching the first conductive film and the third conductive film. Thus, wires using a low resistance material can be formed in a large-sized panel, and thus, a problem of signal delay can be solved.

Abstract: A thin film transistor (TFT) array substrate for an X-ray detector and a method of fabricating the same are provided. The TFT array substrate includes a substrate, a gate line formed on the substrate, a data line crossing the gate line, a thin film transistor including a gate electrode, a source electrode, and a drain electrode, a first electrode connected to the drain electrode, a passivation layer formed over the gate line, the data line, the thin film transistor and the first electrode, a photoconductor formed over the passivation layer and connected to the first electrode, and a second electrode formed on the photoconductor.

Abstract: A semiconductor device includes an insulation interlayer and an etch stop layer sequentially stacked on a substrate wherein a lower structure including a first contact pad is formed. A second contact pad penetrates the insulation interlayer and the etch stop layer and is connected to the first contact pad. The second contact pad protrudes from the etch stop layer. A pad spacer is provided between the second contact pad and the insulation interlayer. A lower electrode is provided on the etch stop layer and is connected to the second contact pad. A dielectric layer and an upper electrode are sequentially provided on the lower electrode.

Abstract: A nitride semiconductor substrate and a method for manufacturing the same are provided. The nitride semiconductor substrate includes an epitaxy substrate, a nitride pillar layer, a nitride semiconductor layer, and a mask layer. The nitride pillar layer includes a plurality of first patterned arranged pillars and a plurality of second patterned arranged pillars. The nitride pillar layer is formed on the epitaxy substrate. A width of a cross-section of each of the second patterned arranged pillars is smaller than a width of a cross-section of each of the first patterned arranged pillars, and a distance among each of the second patterned arranged pillars is longer than a distance among each of the first patterned arranged pillars. Surfaces of the epitaxy substrate, the first patterned arranged pillars, and the second patterned arranged pillars are covered by the mask layer. The nitride semiconductor layer is formed on the nitride pillar layer.

Abstract: A semiconductor device includes a semiconductor layer having a channel region, an impurity layer having a source region and a drain region, and a gate electrode provided so as to face the semiconductor layer with a gate insulating film interposed therebetween. The semiconductor layer has a layered structure of at least a first amorphous film and a crystalline film including a crystal phase, and the first amorphous film is formed directly on the gate insulating film.

Abstract: A unified test structure which is applicable for all levels of a semiconductor device including a current path chain having a first half chain and a second half chain, wherein each half chain comprises lower metallization segments, upper metallization segments, an insulating layer between the lower metallization segments and the upper metallization segments, and connection segments. Each of the connection segments is electrically connected to a contact region of one of the lower metallization segments and to a contact region of one of the upper metallization segments to thereby electrically connect the respective lower metallization segment and the respective upper metallization segment, and the first half chain and the second half chain are of different configuration.

Abstract: A semiconductor graphene is used for a channel layer, and a metal graphene is used for electrode layers for a source, a drain, and a gate which serve as interconnections as well. An oxide is used for a gate insulating layer. The channel layer and the electrode layers are located on the same plane.

Abstract: A semiconductor device includes a semiconductor layer on an insulating layer, and a first partially depleted transistor and a first diode in the semiconductor layer. The first transistor has a first gate electrode above the semiconductor layer via an insulating film and a first source or drain of a first conductivity type in the semiconductor layer below both sides of the gate electrode. The first diode has a first impurity layer of a second conductivity type in a shallow portion of the semiconductor layer and a second impurity layer of the first conductivity type in a deep portion of the semiconductor layer. The first and second impurity layers are stacked in a depth direction of the semiconductor layer. The side surfaces of the first and second impurity layers contact the semiconductor layer just below the first gate electrode.