Abstract: Keep out zones (KOZ) are formed for a through silicon via (TSV). A device can be placed outside a first KOZ of a TSV determined by a first performance threshold so that a stress impact caused by the TSV to the device is less than a first performance threshold while the first KOZ contains only those points at which a stress impact caused by the TSV is larger than or equal to the first performance threshold. A second KOZ for the TSV can be similarly formed by a second performance threshold. A plurality of TSVs can be placed in a direction that the KOZ of the TSV has smallest radius to a center of the TSV, which may be in a crystal orientation [010] or [100]. A plurality of TSV stress plug can be formed at the boundary of the overall KOZ of the plurality of TSVs.

Abstract: A semiconductor device includes a semiconductor substrate and a plurality of gate electrodes including a part extended in a first direction in a plane parallel with the semiconductor substrate. The semiconductor substrate has a second semiconductor layer including a plurality of first conductive type pillars and second conductive type second pillars that are disposed on the first semiconductor layer, extending in the first direction in the plane parallel with the semiconductor substrate and in a third direction intersecting with a second direction orthogonal to the first direction, and arranged adjacent to each other in an alternate manner.

Abstract: The present invention provides a thin film transistor including an oxide semiconductor layer (4) for electrically connecting a signal electrode (6a) and a drain electrode (7a), the an oxide semiconductor layer being made from an oxide semiconductor; and a barrier layer (6b) made from at least one selected from the group consisting of Ti, Mo, W, Nb, Ta, Cr, nitrides thereof, and alloys thereof, the barrier layer (6b) being in touch with the signal electrode (6a) and the oxide semiconductor layer (4) and separating the signal electrode (6a) from the oxide semiconductor layer (4). Because of this configuration, the thin film transistor can form and maintain an ohmic contact between the first electrode and the channel layer, thereby being a thin film transistor with good properties.

Abstract: According to one embodiment, a semiconductor light emitting device includes an n-type semiconductor layer, a p-type semiconductor layer, and a light emitting portion. The light emitting portion is provided between the semiconductor layers and includes barrier layers and well layers alternately stacked. An n-side end well layer which is closest to the n-type semiconductor layer contains InwnGa1-wnN and has a layer thickness twn. An n-side end barrier layer which is closest to the n-type semiconductor layer contains InbnGa1-bnN and has a layer thickness tbn. A p-side end well layer which is closest to the p-type semiconductor layer contains InwpGa1-wpN and has a layer thickness twp. A p-side end barrier layer which is closest to the p-type semiconductor contains InbpGa1-bpN and has a layer thickness tbp. A value of (wp×twp+bp×tbp)/(twp+tbp) is higher than (wn×twn+bn×tbn)/(twn+tbn) and is not higher than 5 times (wn×twn+bn×tbn)/(twn+tbn).

Abstract: The present disclosure provides a resistive random access memory (RRAM) cell. The RRAM cell includes a transistor, a bottom electrode adjacent to a drain region of the transistor and coplanar with the gate, a resistive material layer on the bottom electrode, a top electrode on the resistive material layer, and a conductive material connecting the bottom electrode to the drain region.

Abstract: A method for forming a conformal, homogeneous dielectric film includes: forming a conformal dielectric film in trenches and/or holes of a substrate by cyclic deposition using a gas containing a silicon and a carbon, nitrogen, halogen, hydrogen, and/or oxygen, in the absence of a porogen gas; and heat-treating the conformal dielectric film and continuing the heat-treatment beyond a point where substantially all unwanted carbons are removed from the film and further continuing the heat-treatment to render substantially homogeneous film properties of a portion of the film deposited on side walls of the trenches and/or holes and a portion of the film deposited on top and bottom surfaces of the trenches and/or holes.

Abstract: A method of making a two-dimensional detector array (and of such an array) comprising, for each of a plurality of rows and a plurality of columns of individual detectors, forming an n-doped semiconductor photo absorbing layer, forming a bather layer comprising one or more of AlSb, AlAsSb, AlGaAsSb, AlPSb, AlGaPSb, and HgZnTe, and forming an n-doped semiconductor contact area.

Abstract: A semiconductor light emitting element (1) including of a substrate (110) composed of sapphire; a laminated semiconductor layer (100) composed of an n-type semiconductor layer (140), a light emitting layer (150) and a p-type semiconductor layer (160) provided on the substrate (110); a first electrode (170) formed in the p-type semiconductor layer (160); and a second electrode (180) formed in the n-type semiconductor layer (140). Further, the first electrode (170) includes a first conductive layer (171) composed of an oxide transparent conductive material laminated on the p-type semiconductor layer (160); a reflection layer (172) which contains silver laminated on the first conductive layer (171); a second conductive layer (173) composed of an oxide conductive material laminated on the reflection layer (172); and a coating layer (174) provided so as to cover the first conductive layer (171), the reflection layer (172) and the second conductive layer (173).

Abstract: Disclosed herein are various methods of forming FinFET semiconductor devices so as to tune the threshold voltage of such devices. In one example, the method includes forming a plurality of spaced-apart trenches in a semiconducting substrate to define at least one fin (or fins) for the device, prior to forming a gate structure above the fin (or fins), performing a first epitaxial growth process to grow a first semiconductor material on exposed portions of the fin (or fins) and forming the gate structure above the first semiconductor material on the fin (or fins).

Abstract: The present application discloses a semiconductor device comprising a source region and a drain region in an ultra-thin semiconductor layer; a channel region between the source region and the drain region in the ultra-thin semiconductor layer; a front gate stack above the channel region, the front gate comprising a front gate and a front gate dielectric between the front gate and the channel region; and a back gate stack below the channel region, the back gate stack comprising a back gate and a back gate dielectric between the back gate and the channel region, wherein the front gate is made of a high-Vt material, and the back gate is made of a low-Vt material. According to another embodiment, the front gate and the back gate are made of the same material, and the back gate is applied with a forward bias voltage during operation. The semiconductor device alleviates threshold voltage fluctuation due to varied thickness of the channel region by means of the back gate.

Abstract: A light-emitting device production method includes a positioning step of positioning, in a light-emitting element, a sealing member at least containing a silicone resin semi-cured at a room temperature (T0) by primary cross-linking and a fluorescent material, the silicone resin decreasing in viscosity reversibly in a temperature region between the room temperature (T0) and a temperature lower than a secondary cross-linking temperature (T1), and being totally cured non-reversibly in a temperature region equal to or higher than the secondary cross-linking temperature (T1).

Abstract: Radiation detectors and methods of fabricating radiation detectors are provided. One method includes mechanically polishing at least a first surface of a semiconductor wafer using a polishing sequence including a plurality of polishing steps, wherein a last polishing step of the polishing sequence includes polishing with a slurry having a grain size smaller than about 0.1 ?m to create a polished first surface. The method also includes applying (i) an encapsulation layer on a top of the polished first surface to seal the polished first surface and (ii) a photoresist layer on top of the encapsulation layer on the polished first surface. The method further includes creating undercuts of the encapsulation layer under the photoresist layer. The method additionally includes partially etching the polished first surface of the semiconductor via the openings in the photoresist layer and in the encapsulation layer to partially etch the semiconductor creating etched regions.

Abstract: A semiconductor structure includes a carrier, a first protective layer, a second protective layer, and a third protective layer. A first surface of the first protective layer comprises a first anti-stress zone. A first extension line from a first bottom edge intersects with a second extension line from a second bottom edge to form a first base point. A first projection line is formed on the first surface, an extension line of the first projection line intersects with the second bottom edge to form a first intersection point, a second projection line is formed on the first surface, and an extension line of the second projection line intersects with the first bottom edge to form a second intersection point. A zone by connecting the first base point, the first intersection point and the second intersection point is the first anti-stress zone.

Abstract: A device used as an ESD protection structure, which is a modified N-type LDMOS device is disclosed. A conventional LDMOS includes only one N-type heavily doped region as a drain in an N-type lightly doped region (11), while the device of the invention includes a P-type heavily doped region (22) in an N-type lightly doped region (11), dividing the N-type heavily doped region into two N-type heavily doped regions (21, 23) unconnected and independent to each other. The N-type heavily doped region (21) close to the gate (14) has no picking-up terminal. The N-type heavily doped region (23) away from the gate (14) together with the P-type heavily doped region (22) is picked up and connected to an input/output bonding pad.

Abstract: A method and structure for a three-axis magnetic field sensing device. An IC layer having first bond pads and second bond pads can be formed overlying a substrate/SOI member with a first, second, and third magnetic sensing element coupled the IC layer. One or more conductive cables can be formed to couple the first and second bond pads of the IC layer. A portion of the substrate member and IC layer can be removed to separate the first and second magnetic sensing elements on a first substrate member from the third sensing element on a second substrate member, and the third sensing element can be coupled to the side-wall of the first substrate member.

Abstract: A thin film transistor for an organic light emitting display device is disclosed. In one embodiment, the thin film transistor includes: a substrate, an active layer formed over the substrate, wherein the active layer is formed of an oxide semiconductor, a gate insulating layer formed over the substrate and the active layer, and source and drain electrodes formed on the gate insulating layer and electrically connected to the active layer. The transistor may further include a gate electrode formed on the gate insulating layer and formed between the source and drain electrodes, wherein the gate electrode is spaced apart from the source electrode so as to define a first offset region therebetween, and wherein the gate electrode is spaced apart from the drain electrode so as to define a second offset region therebetween.

Abstract: An object is to improve reliability of a light-emitting device. A light-emitting device has a driver circuit portion including a transistor for a driver circuit and a pixel portion including a transistor for a pixel over one substrate. The transistor for the driver circuit and the transistor for the pixel are inverted staggered transistors each including an oxide semiconductor layer in contact with part of an oxide insulating layer. In the pixel portion, a color filter layer and a light-emitting element are provided over the oxide insulating layer. In the transistor for the driver circuit, a conductive layer overlapping with a gate electrode layer and the oxide semiconductor layer is provided over the oxide insulating layer. The gate electrode layer, a source electrode layer, and a drain electrode layer are formed using metal conductive films.

Abstract: A method for manufacturing a distributed feedback laser array includes: forming a bottom separate confinement layer on a substrate; forming a quantum-well layer on the bottom separate confinement layer; forming a selective-area epitaxial dielectric mask pattern on the quantum-well layer; forming a top separate confinement layer on the quantum-well layer through selective-area epitaxial growth using the selective-area epitaxial dielectric mask pattern, the top separate confinement layer having different thicknesses for different laser units; removing the selective-area epitaxial dielectric mask pattern; forming an optical grating on the top separate confinement layer; and growing a contact layer on the optical grating. The present disclosure achieves different emission wavelengths for different laser units without significantly affect emission performance of the quantum-well material.

Abstract: The invention concerns a silicon devices/heatsinks stack assembly and a method to pull apart a faulty silicon device in said stack assembly. Said silicon devices/heatsinks stack assembly comprises an arrangement of many silicon devices disks, two adjacent silicon devices disks being separated by a flat heatsink device, each silicon device disk and each heatsink comprising a centering hole on its both faces, a centering pin placed between the adjacent centering holes of a silicon device disk and an adjacent heatsink device. Each heatsink device is pierced with two guide holes, at two opposite ends of this one.

Abstract: Three dimension memory arrays and methods of forming the same are provided. An example three dimension memory array can include a stack comprising a plurality of first conductive lines separated from one another by at least an insulation material, and at least one conductive extension arranged to extend substantially perpendicular to the plurality of first conductive lines, such that the at least one conductive extension intersects a portion of at least one of the plurality of first conductive lines. Storage element material is formed around the at least one conductive extension. Cell select material is formed around the at least one conductive extension.