Abstract: Systems and methods for handling node policies in a firmware framework. In some embodiments, an Information Handling System (IHS) may include a controller, where the controller comprises firmware that, upon execution by a processing core, causes the processing core to instantiate an orchestrator; and a plurality of devices coupled to the controller, where each device comprises firmware that, upon execution by a corresponding processing core, causes the corresponding processing core to instantiate a node as part of a firmware framework, and where the orchestrator is configured to distribute a policy to at least a given node without any involvement by any Operating System (OS) of the IHS.

Abstract: A data storage device and method are disclosed for transaction recovery using extra timeout. In one embodiment, a data storage device is provided comprising a memory and one or more processors. The one or more processors, individually or in combination, are configured to: receive a command from a host, wherein the command is associated with a timeout window; begin processing the command; and after beginning processing the command but prior to expiration of the timeout window: determine that the command will not be completed prior to expiration of the timeout window; and send a request to the host for an extension of the timeout window. Other embodiments are provided.

Abstract: Data storage systems are disclosed. In some implementations, a data storage device includes a controller coupled to a plurality of memory devices to control memory operations of the plurality of memory devices, and including M communication lanes, and an interface device configured to include N communication lanes to be connected to a host device that includes N communication lanes and to the M communication lanes of the controller, wherein the interface device includes a connector configured to connect the N communication lanes of the host device to the N communication lanes of the interface device, and a selector configured to, in response to a host port type identification signal received from the host device, selectively activate M communication lanes of the interface device, out of the N communication lanes of the interface device, to transmit or receive the data to or from the M communication lanes of the controller.

Abstract: Noise immunity of a protocol determination circuit that determines a communication protocol between circuits is improved. A protocol determination circuit includes: a sampling circuit; and a majority decision circuit. The sampling circuit performs a plurality of number of times of sampling on a protocol specifying signal, the protocol specifying signal being any one of a value indicating a first communication protocol I2C and a value indicating a second communication protocol SPI. The majority decision circuit outputs a majority decision signal, the majority decision signal indicating a communication protocol corresponding to a value sampled majority number of times in the plurality of number of times of sampling.

Abstract: PAM encoding techniques that leverage unused idle periods in channels between data transmissions to apply longer but more energy-efficient codes. To improve energy savings, multiple sparse encoding schemes may be utilized selectively to fit different sized gaps in the traffic. These approaches may provide energy reductions, for example with memory READ and WRITE traffic, when transferring 4-bit data using 3-symbol sequences.

Abstract: Methods and systems for managing a data processing system are disclosed. A management controller installed within the data processing system that operates independently from a central processing unit (CPU) (e.g., a motherboard) of the data processing system may manage access of the data processing system to various peripheral devices. The peripheral devices may be connected to the data processing system via a compute express link (CXL) switch. Other data processing systems may also be connected to the peripheral devices via the CXL switch, creating a shared environment where the capabilities and functionalities of the peripheral devices can be shared between these data processing systems.

Abstract: A stream switch includes a data router, configuration registers, and arbitration logic. The data router has a plurality of input ports, each having a plurality of associated virtual input channels, and a plurality of output ports, each having a plurality of associated virtual output channels. The data router transmits data streams from input ports to one or more output ports of the plurality of output ports. The configuration registers store configuration data associated with the virtual output channels of the respective output ports of the plurality of output ports. The stored configuration data identifies a source input port and virtual input channel ID associated with the virtual output channel of the output port. The arbitration logic allocates bandwidth of the data router based on request signals associated with virtual input channels of the input ports and the configuration data associated with the virtual output channels.

Abstract: A control system for a vehicle, device, or asset includes a dock for a mobile device; and a control mechanism coupled, or coupleable to, the dock and including a power input, a dock input, and a first output, wherein the control mechanism defines an second switch position and a first switch position, wherein the switching mechanism is in the first switch position when a power source is coupled to the power input and an enablement signal is received from the dock via the dock input, otherwise the switching mechanism is in the second switch position, wherein the first output is coupleable to the vehicle, device, or asset to allow operation of the vehicle, device, or asset only when the switching mechanism is in the first switch position.

Abstract: An apparatus and a controlling method for a two-wire serial bus are provided. The apparatus is coupled to a host and a plurality of sensors via the two-wire serial bus, and includes a storage member and a control circuit. The storage member is configured to store an event table that includes triggering conditions respectively corresponding to the sensors. The control circuit is coupled to the storage member and configured to periodically query a detection value of each of the sensors in sequence to determine that the detection value of the sensor meets one of the triggering conditions corresponding to the sensor, and to produce a notification signal to the host through the two-wire serial bus according to the determined result; the notification signal indicates the sensor that meets the triggering condition. The host executes a processing program corresponding to the sensor in response to the notification signal.

Abstract: An out-of-band backplane information verification system includes a backplane, a BMC device coupled to the backplane, and a processing system connected to the backplane and providing an operating system. The operating system retrieves in-band backplane information from the backplane, retrieves first out-of-band backplane information from the BMC device during a first time period, and retrieves second out-of-band backplane information from the BMC device during a second time period that is subsequent to the first time period. The operating system then determines that the second out-of-band backplane information does not match the first out-of-band backplane information and, in response, determines that the second out-of-band backplane information does not match the in-band backplane information.

Abstract: A vehicle includes first unit(s), second unit(s), and an intermediate unit. The intermediate unit is configured to mediate communication between the communication device and the first unit(s) or the second unit(s), and include intermediate unit processor(s) and intermediate unit memory(ies) coupled to the intermediate unit processor(s). The intermediate unit processor(s) are configured to: when a first message including a first functional address and a predetermined command is received from a communication device, transmit the first message to the first unit(s); when a second message including a second functional address and the command is received from the communication device, transmit the first message to the first unit(s); when the first message is received from the communication device, transmit the second message to the second unit(s); and when the second message is received from the communication device, transmit the second message including the to the second unit(s).

Abstract: A semiconductor device includes a receiving terminal for receiving a signal transmitted through a signal transmission line, a reference plane voltage terminal connected to a refence plane as a refence for the signal on the signal transmission line and a voltage generating circuit configured to generate a refence plane voltage to be supplied to the reference plane voltage terminal based on the signal received by the receiving terminal.

Abstract: A method for a listening network node is described herein. In accordance with one embodiment, the method includes receiving data from a serial bus interface, wherein the data includes (at least) a first header of a first data frame. The method further includes detecting completion of the reception of the first header and detecting whether the data received subsequent to the first header includes a recessive bit and storing information that indicates whether or not a recessive bit has been detected. Furthermore, the method includes detecting a stop bit in the data received subsequent to the first header and, when the detection of the stop bit fails, detecting a break delimiter that indicates the end of a break field of a second header, signaling a frame error if the stored information indicates that a recessive bit has been received, and signaling a missing response if the stored information indicates that a recessive bit has not been received.

Abstract: A serial bus repeater includes first and second ports adapted to be coupled to respective devices. A first termination resistor network couples to the first port. A second termination resistor network couples to the second port. A squelch detect circuit couples to the first bus port and is configured to detect activity on the first bus and to generate a squelch signal responsive to detection of activity on the first port. A first state machine is configured to: determine an elapsed time during which the squelch signal indicates activity on the first port; determine that the elapsed time exceeds a first threshold; and, responsive to the determination that the elapsed time exceeds the first threshold, assert configuration signals to reconfigure the first and second termination resistor networks.

Abstract: Disclosed is a small computer-system interface (SCSI) device (102) including an initialization unit (110) and a control unit (112), implemented on at least one of, a Field Programmable Gate Array (FPGA) and Application Specific Integrated Circuits (ASICs). The query unit (110) sends a first signal to a slave controller (104), receives, from the Slave controller (104), first information of a peripheral device (106), in response to the first signal, receives second information from the master controller (108). The control unit (112) generates a plurality of command descriptor blocks (CDBs) based on the first information and the second information, and sends the plurality of CDBs to the slave controller (104) for a transfer of data between the master controller (108) and the peripheral device (106), receives the data from the slave controller (104) and send the data to the master controller (108).

Abstract: A dynamic hot backup method, apparatus and device of a server, and a storage medium. Connection modes for connecting a Peripheral Component Interconnect (PCI) link to a hard disk drive is determined by acquiring a bandwidth splitting condition of the PCI link of a device, and hot backup parameters in an advanced configuration and power management interface protocol are correspondingly set according to the connection modes.

Abstract: Systems, methods, and apparatuses are described that enable IC architectures to enable a single anchor to connect to and accept a variety of chiplets at any port by way of a programming model that enables the anchor or chiplet to dynamically adapt to configurations, requirements, or aspects of any coupled component and provide an interface for the coupled components.

Abstract: The present disclosure relates to a method for transmitting data between a first entity and a second entity, and a method for operating an electronic apparatus may include a method for operating an electronic apparatus, including: transmitting a first read enable signal indicating being ready to receive data to an external device; receiving a first data strobe signal indicating start of data transmission and a first data from the external device; receiving subsequent data after the first data from the external device; and receiving a second data strobe signal indicating end of the data transmission and a last data from the external device.

Abstract: There is provided a memory module including a first memory device constituting a first rank, and a second memory device constituting a second rank sharing a command/address signal and a clock signal with the first memory device. The first memory device and the second memory device receive the command/address signal and the clock signal in a matched type, and the first memory device includes a variable delay line for adjusting a delay of the received clock signal.

Abstract: This application relates to a link width adjustment method and apparatus. The method includes: sending, to a second-end apparatus through a first channel, a first packet indicating to perform link width switching; receiving a second packet that is returned by the second-end apparatus and that indicates that the link width switching is agreed on; sending, to the second-end apparatus through a second channel, a first bit stream to test the second channel for data communication; and sending a data stream to the second-end apparatus through the first channel and the second channel.