Abstract: An Inter-Integrated Circuit (I2C) deadlock and recovery method and apparatus include the following steps: providing an optical module reading unit and an optical module isolation unit in a CPU of a switch; configuring the optical module reading unit to periodically scan the states of each optical module in the switch, reading contents of in-place optical modules, determining whether there is an optical module in which a content reading failure occurs but the state of which is in place, and if there is, determining that there is a faulty optical module; and configuring the optical module isolation unit to isolate all the optical modules of the switch, resetting an I2C bus, searching for and blocking the faulty optical module, deactivating the isolation of normal optical modules in the switch after the faulty optical module is blocked off, and notifying a BMC before and after the isolation of the optical modules.

Abstract: According to an aspect, there is provided a method for determining a sequence of bus nodes in a multi-drop communication bus. The method includes for each bus node: sending a request to the bus node using an bus node physical identifier to set the bus node to a loopback mode; transmitting at least one signal to the bus node via the multi-drop communication bus; receiving from the bus node a loopback signal caused by the at least one signal; and measuring a roundtrip delay between the at least one signal and the loopback response signal. The method further includes solving the physical order of the bus nodes in the multi-drop communication bus based on the roundtrip delays.

Abstract: Disclosed are an SPI controller and a method of operating an SPI controller. The SPI controller includes: an SPI clock signal generator; a register group configured to store SPI operating configuration of the SPI controller; SPI pins configured to connect to one or more SPI peripherals; and an input/output controller configured to perform data input or output between the SPI controller and the SPI peripherals according to the SPI clock signal and the SPI operating configuration; an SPI state machine configured to control a working state of the SPI controller. The SPI controller is electrically coupled via a bus to a CPU, a DMA controller, and a system memory located outside the SPI controller; and the input/output controller is further configured to receive an updated SPI operating configuration from the DMA controller and to update the updated SPI operating configuration into the register group between two consecutive SPI transmissions.

Abstract: A system (e.g., a power and communication system for remote components) can include a first wire, a second wire, and a first module operatively connected to the first and second wire. The first module can be configured to output power to and to communicate over the first wire and second wire. The system can include a second module operatively connected to the first module by the first wire and the second wire. The second module can be configured to receive power from the first module and to communicate with the first module over the first wire and/or second wire. The first module can be configured to modify a voltage on at least the first wire to signal to the second module to provide serial communication to the first module via the first wire and/or second wire.

Abstract: A USB controller includes: a USB interface that receives an isochronous timestamp packet (ITP) from a host device that includes a current time value from the host device and a delay value associated with each hub through which the ITP passed; controller hardware that initiates a counter, sends a link delay measurement (LDM) link management packet (LMP) request to a nearest upstream hub, stores a first timestamp that corresponds to when the LDM LMP request was sent, receives an LDM LMP response from the nearest upstream hub, and stores a second timestamp that corresponds to when the LDM LMP response was received; and controller software that calculates a link delay between the USB controller and the nearest upstream hub based on the first and second timestamps and delay information included in the LDM LMP response, and adjusts the counter value based on the calculated link delay.

Abstract: A method includes programming first and second values and a first compare enable command into respective first operand, second operand, and first compare enable command registers in a hardware comparator circuit. The method includes determining that a first match exists corresponding to the first and second values, programming a third value into the first operand register and a fourth value into the second operand register, and programming a second compare enable command into a second compare enable command register in the hardware comparator circuit. In response to a determination that a second match exists corresponding to the third and fourth values, the method includes asserting a success interrupt signal, programming a fifth value into the first operand register and a sixth value into the second operand register and programming a second compare enable command into a second compare enable command register in the hardware comparator circuit.

Abstract: An image processing apparatus that is capable of extending a function while guaranteeing performance and quality. The image processing apparatus has a USB host controller. A first USB host interface is installed inside the image processing apparatus. A storage unit stores device information about a USB storage device that can be used as a system storage device of the image processing apparatus. A memory device stores a set of instructions. A processor executes the set of instructions to obtain individual identification information about a USB storage device from the USB storage device in a case where the USB storage device is connected to the first USB host interface, and control to achieve a state where the USB storage device is available as the system storage device of the image processing apparatus in a case where the individual identification information is in the device information.

Abstract: Provided are a data transmission control method and device and a non-transitory computer-readable medium. The data transmission control method includes: determining a multiple and a remainder according to a total data size of to-be-transmitted data and a set byte size, where the multiple is equal to a quotient obtained by dividing the total data size by the set byte size, and the remainder is equal to a remainder obtained by dividing the total data size by the set byte size; sequentially transmitting data whose size is the set byte size multiplied by the multiple in the to-be-transmitted data by transmitting data of the set byte size each time; and in response to the remainder being not zero, transmitting remaining data whose size is the remainder in the to-be-transmitted data.

Abstract: Disclosed are a multi-mode virtual serial port chip, an implementation method, and a firmware downloading system and method thereof. The multi-mode virtual serial port chip comprises a normal operating mode and an enhanced operating mode, which are selected by a multiplexed auxiliary signal pin according to that whether there is a pull-down resistor connected thereto. The normal operating mode is compatible with the prior art and applications, and one-click automatic MCU firmware downloading can also be realized in the enhanced operating mode. In the present invention, no peripheral circuit is needed, the MCU also cannot unintentionally enter other modes, and the effects of automatically downloading firmware, improving downloading efficiency, reducing costs, reducing power consumption and decreasing product volume are achieved.

Abstract: A PCIe resource management system includes a PCIe resource registration subsystem and a PCIe resource monitoring subsystem. Assets register to use PCIe resources of other assets and to allow other assets to use their PCIe resources. Assets specify which types of PCIe resources it can borrow, when it can borrow those PCIe resources, and a logical group of other assets from which the asset can borrow the PCIe resources. Assets also specify which types of PCIe resources it will lend, when it will lend those PCIe resources, and a logical group of other assets to which the asset will lend the PCIe resources. The PCIe resource registration subsystem maintains a PCIe resource registration datastore maintaining PCIe borrow and lending rules associated with assets in logical groups of assets. PCIe resources are shared between assets in the logical groups as needed, as determined by the PCIe resource monitoring subsystem.

Abstract: Methods for USB signal communication over an optical link are described. One aspect includes detecting connection of a device circuit to a USB device. The detecting may further include transmitting an electrical pulse through a reactive network, and detecting a change in a delay associated with the electrical pulse responsive to connecting the device circuit to the USB device. An optical signal associated with the detected connection may be transmitted to a host circuit via an optical communication channel.

Abstract: Various embodiments include a network for transmitting data words from a source node to a destination node. The source node optionally inverts the logic levels of each data word so that the number of logic ‘1’ bits in each data word is less than or equal to half of the data bits. The destination node recovers the original data words by passing the data words not inverted by the source node and inverting the data words that were inverted by the source node. As the packet is transmitted through the network, each node encodes and/or decodes the data words by generating an output transition for each logic ‘1’ bit of the input data word. Because no more than half the bits of the input data word are logic ‘1’ bits, the node generates output transitions for no more than one half of the data bits.

Abstract: An embedded USB2 (eUSB2) repeater includes an eUSB2 port having first and second terminals. The eUSB2 port facilitates two-way communication between the repeater and an application processor unit (APU) according to voltage level specifications for eUSB2. The repeater includes a USB port having first and second terminals. The USB port facilitates two-way communication between the repeater and a Universal Asynchronous Receiver Transmitter (UART) according to voltage level specifications for US. The repeater includes a multiplexer having an input coupled to receive a control signal. The multiplexer selectively establishes connections between the first and second terminals of the eUSB2 port and the first and second terminals of the USB port.

Abstract: According to an embodiment, a shift register parallelizes a serial data signal serving to transfer data including multiple symbols on the basis of a first clock. A first circuit generates, on the basis of the first clock, a second clock being a clock signal for transferring a parallel data signal having a width of the first number of bits. A first flip-flop group sequentially fetches data of the first number of bits from the serial data signals parallelized by the shift register on the basis of the second clock. The first flip-flop group then outputs the fetched data of the first number of bits as a parallel data signal. A second circuit adjusts a phase of the second clock such that the first flip-flop group fetches data of the first number of bits beginning with bit data located at a head of each symbol of the multiple symbols.

Abstract: A serial bus repeater includes first and second ports adapted to be coupled to respective devices. A first termination resistor network couples to the first port. A second termination resistor network couples to the second port. A squelch detect circuit couples to the first bus port and is configured to detect activity on the first bus and to generate a squelch signal responsive to detection of activity on the first port. A first state machine is configured to: determine an elapsed time during which the squelch signal indicates activity on the first port; determine that the elapsed time exceeds a first threshold; and, responsive to the determination that the elapsed time exceeds the first threshold, assert configuration signals to reconfigure the first and second termination resistor networks.

Abstract: The present disclosure provides a port controller and an electronic device. The port controller is compatible with a Universal Serial Bus (USB) Type-C standard and is used in a device operable as a sink device. The port circuit is communicable with an external main controller. A transceiver is communicable with a source device via a configuration channel (CC) pin of a receptacle. A control unit is capable of negotiating with the source device via the transceiver. A pin control circuit controls a state of the CC pin and monitors the state of the CC pin. A power supply circuit receives a bus voltage supplied from the source device and generates a power supply voltage of the main controller.

Abstract: Techniques in electronic systems, such as in systems comprising a CPU die and one or more external mixed-mode (analog) chips, may provide improvements advantages in one or more of system design, performance, cost, efficiency and programmability. In one embodiment, the CPU die comprises at least one microcontroller CPU and circuitry enabling the at least one CPU to have a full and transparent connectivity to an analog chip as if they are designed as a single chip microcontroller, while the interface design between the two is extremely efficient and with limited in number of wires, yet may provide improved performance without impact to functionality or the software model.

Abstract: A data transmission method, apparatus, and device and a storage medium. A control instruction sent by a first node main program is received and analyzed; when the control instruction is analyzed to be a first control instruction for controlling a first node, a value is assigned to a first variable of the first node; the first control instruction is executed to obtain first result data and fed back same to the first node main program; the first variable of the first node is sent to a second node SES program, so that the second node SES program receives and analyzes same, and assigns a value to a second variable of a second node. According to the method, in a multi-controller data processing situation, node data transmission is increased, redundant link control of a two-node SES program by one node is implemented, and an information interaction redundancy mechanism can be enhanced.

Abstract: An integrated circuit, and a data processing device and method are provided. The integrated circuit includes a processor circuit and an accelerator circuit. The processor circuit includes a processor, a first data storage section, and a first data input/output interface. The accelerator circuit includes an accelerator and a second data input/output interface. The second data input/output interface is electrically connected to the first data input/output interface, so that the accelerator circuit can perform information interaction with the first data storage section.

Abstract: A Peripheral Component Interconnect Express (PCIe) device performing communication with a host through a PCIe link includes a first physical function, a plurality of second physical functions, and a function mode controller. The first physical function manages the PCIe link and receives function mode control information from the host. Each of the plurality of second physical functions may be enabled or disabled according to a respective operation mode. Based on the function mode control information, the function mode controller sets the operation modes of the plurality of second physical functions to one of an active mode and an inactive mode.