Abstract: A high-bandwidth memory (HBM) includes a memory and a controller. The controller receives a data write request from a processor external to the HBM and the controller stores an entry in the memory indicating at least one address of data of the data write request and generates an indication that a data bus is available for an operation during a cycle time of the data write request based on the data write request comprising sparse data or data-value similarity. Sparse data includes a predetermined percentage of data values equal to zero, and data-value similarity includes a predetermined amount of spatial value locality of the data values. The predetermined percentage of data values equal to zero of sparse data and the predetermined amount of spatial value locality of the special-value pattern are both based on a predetermined data granularity.

Abstract: A port multiplier for extending ports of a radio communication test instrument comprises an input for receiving at least one input signal, a power supply unit, a control logic, and at least one output for outputting a processed signal. The port multiplier is configured to split the at least one input signal into its different components such that a radio signal component of the input signal is forwarded to the at least one output. A power signal component of the input signal is forwarded to the power supply unit. Further, a control signal component of the input signal is forwarded to the control logic. Moreover, a radio communication test system for testing a device under test is described.

Abstract: A computer system includes a BMC and a host of the BMC. The BMC receives a first message from a first remote device on a management network. The BMC determines whether the first message is directed to a storage service or fabric service executed on a main processor of a storage controller of the host. The host is a storage device. The storage controller includes an RDMA controller in communication with the main processor through an internal communication channel of the storage controller. The RDMA controller is managed by the storage service. The BMC extracts a service management command from the first message, when the first message is directed to the storage service or fabric service. The BMC sends, through a BMC communication channel established for communicating baseboard management commands between the BMC and the host, a second message containing the service management command to the host.

Abstract: A processing element/unit can include a plurality of networks, a plurality of cores, crossbar interconnects, a plurality of memory controllers and local memory on an integrated circuit (IC) chip. The plurality of cores can be coupled together by the plurality of networks on chip. The crossbar interconnects can couple the networks of cores to the plurality of memory controllers. The plurality of memory controllers can be configured to access data stored in off-chip memory. The local memory can be configured to cache portions of the accessed data. The local memory can be directly accessible by the network of processing cores, or can be distributed across the plurality of memory controllers. The memory controllers can be narrow channel (NC) memory controllers having widths of 4, 8, 12, 16 or a multiple of 4 bits.

Abstract: A domestic appliance includes a heating element, a user interface for receiving user input, and a main controller. The main controller is in operative communication with the user interface via a touchscreen controller. The main controller is also in operative communication with the heating element. The user interface is in operative communication with the heating element via the touchscreen controller and the main controller. The user interface is in operative communication with the touchscreen controller via an inter-integrated circuit bus. The domestic appliance also includes a serial peripheral interface monitor in operative communication with the inter-integrated circuit bus. The appliance may be configured for, and related methods may include, receiving and monitoring, by the serial peripheral interface monitor, communication between the user interface and the touchscreen controller over the inter-integrated circuit bus.

Abstract: A dock system is provided. The dock system includes a dock device and an electronic device. The dock device includes a first connection interface, a Power Delivery (PD) controller, a storage device, and a plurality of connection ports. The PD controller is coupled to the connection ports. The electronic device includes a second connection interface and a processor. In response to the first connection interface being connected to the second connection interface, the processor executes a high-layer service filter driver to write system information corresponding to the electronic device into the storage device, and the PD controller uses the system information to set the parameters of the connection ports. The first connection interface and the second connection interface are PD interfaces.

Abstract: Systems and methods for controlling data transaction between master and slave devices are described. A master device can be connected to multiple slave devices that can operate under one of a first, a second, and a third operation modes. The first operation mode can cause the master device to perform data transactions with the multiple slave devices via a network element and the multiple slave devices can be connected to one another via the network element. The second operation mode can disconnect the master device from the multiple slave devices, and multiple agents connected to the multiple slave devices can fulfill the data transactions. The third operation mode can cause the master device to perform data transactions with a first subset of the multiple slave devices via the network element, and can cause the master device to be disconnected from a second subset of the multiple slave devices.

Abstract: A system for controlling a process having a first control device for processing first data, and a first communication interface of a first communication unit designed for receiving the first data, and a second control device for processing second data, and a second communication interface of a second communication unit, designed for receiving the second data. The first communication unit comprises a third communication interface and the second communication unit comprises a fourth communication interface. The third communication interface is connected to the second communication interface and the first processor processes or compares the second data received by the third communication interface with the first data received by the first communication interface.

Abstract: A device includes an interconnect and a plurality of devices connected to the interconnect. The plurality of devices includes a first interface connected to the interconnect and a second interface connected to the interconnect. The plurality of devices further includes a first memory bank connected to the interconnect and a second memory bank connected to the interconnect. The plurality of devices further includes an external memory interface connected to the interconnect and a controller configured to establish virtual channels among the plurality of devices connected to the interconnect.

Abstract: A programmable controller includes a plurality of modules arranged along a predetermined arrangement direction, and the plurality of modules includes a master station module and slave station modules. The programmable controller includes a main line configured to provide communication between the master station module and the slave station modules, and sub-lines configured to provide communication between two adjacent modules. The programmable controller sets station numbers of the slave station modules by communication via the sub-lines, and then performs communication via the main line using the set station numbers.

Abstract: A semiconductor memory device includes a substrate that has a first main surface and a second main surface opposite to the first main surface, a first semiconductor chip which is mounted on the first main surface and includes a first register, a plurality of first input/output (IO) terminals, and a first circuit connected between the first IO terminals and the first register, and a second semiconductor chip which is mounted on the second main surface and includes a second register, a plurality of second input/output (IO) terminals, and a second circuit connected between the second IO terminals and the second register. The second circuit is connected to the second IO terminals through input lines and to the second register through output lines, and is configured to change a connection path between the input lines and the output lines in response to a connection change command.

Abstract: Example implementations relate to safe peripheral device communications. In one example, a host computing device can include a serializer/deserializer (SERDES), a PCIe bus, a video source, a connector coupled, via the SERDES, to the PCIe bus and the video source; and a host controller to operate in a safe mode and cause PCIe data from PCIe bus to be provided, via the SERDES and the connector, solely to a peripheral controller of a peripheral device.

Abstract: Techniques for emulating a configuration space by a peripheral device may include receiving a access request, determining that the access request is for an emulated configuration space of the peripheral device, and retrieving an emulated configuration from an emulated configuration space. The access request can then be serviced by using the emulated configuration.

Abstract: An integrated communication unit includes a motherboard, at least one RJ45 interface and an SPI. The motherboard includes a microcontroller that has a middleware. The RJ45 interface provides a cable-based connection to an external control unit. The SPI interface couples to a further SPI interface of an application unit. The SPI interface is configured for receiving application data of the application unit and provides the application data to the microcontroller by transmission. The microcontroller is configured to process the application data and provide the application data to an external control unit via the RJ45 interface. The integrated communication unit is configured to be mounted on a printed circuit board of the application unit by THT or SMT.

Abstract: Distributed processors and methods for compiling code for execution by distributed processors are disclosed. In one implementation, a distributed processor may include a substrate; a memory array disposed on the substrate; and a processing array disposed on the substrate. The memory array may include a plurality of discrete memory banks, and the processing array may include a plurality of processor subunits, each one of the processor subunits being associated with a corresponding, dedicated one of the plurality of discrete memory banks. The distributed processor may further include a first plurality of buses, each connecting one of the plurality of processor subunits to its corresponding, dedicated memory bank, and a second plurality of buses, each connecting one of the plurality of processor subunits to another of the plurality of processor subunits.

Abstract: An accessory interface (100) for an electronic accessory is provided. The accessory interface includes a microprocessor (102) that provides selectable data functionality. A configuration memory (106) is coupled to a connector (104) of the accessory interface via a unidirectional configuration interface (108). The unidirectional configuration interface indicates the selectable data functionality to a portable radio. The portable radio presents data connectivity signals to first and second GPIO pins of the connector which represent either valid or invalid data configuration states. The configuration state is presented to a single ended one (SE1) input port of the microprocessor. The microprocessor selects a data connectivity mode of operation in response to valid and invalid configurations being presented to the SE1 port. An accessory incorporating the accessory interface is able to interchangeably connect to different radios supporting different data connectivity modes of operation.

Abstract: Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, an integrated circuit (IC) memory device is disclosed. The memory device includes an array of storage cells and command interface circuitry to receive an internal transfer command. In response to the internal transfer command, transfer logic reads data from a first portion of the array of storage cells, transfers the data as on-chip transfer data, and writes the on-chip transfer data to a second portion of the array of storage cells. In response to the command interface circuitry receiving an interrupt command, the transfer logic pauses the internal transfer operation, and carries out an unrelated memory access operation involving at least the first portion of the array of storage cells or the second portion of the array of storage cells.

Abstract: An apparatus includes a processor, a first interface configured to connect to a bus of the apparatus, a second interface configured to communicate over a packet network, and circuitry. The circuitry is configured to, in a first operational mode, exchange data between the processor and one or more remote devices over the packet network, via the second interface, and in a second operational mode, monitor the bus using the first interface, detect a predefined trigger event occurring on the bus and, in response to detecting the trigger event, log one or more transactions on the bus that are adjacent to the trigger event and generate one or more protocol-analysis packets comprising at least part of the logged transactions.

Abstract: A computer-implemented method according to one embodiment includes receiving, at a peripheral device via an in-band interface, a predetermined command; determining, by the peripheral device, a predetermined identifier within the predetermined command; and implementing, by the peripheral device, parameter data associated with the predetermined identifier, in response to the determining.

Abstract: A system for determine presence or quality of an external timing device is provided. The system may include a circuit (e.g., in a field-programmable gate array (FPGA)) having an input, an oscillator, an edge detector, a bit counter, and a calculator element. In some examples, the input may receive an input signal under test. The oscillator may advance a timer at a known rate to facilitate generation of clock samples for the input signal under test. The edge detector may measure edges of the input signal under test based on the clock samples. The circuit may include at least one bit counter to store a count associated with the measured edges for a shorter interval timer period and a longer interval timer period. The calculator element may determine presence or quality of an external timing device based on the count.