Abstract: Methods and systems are disclosed for an upstream facing port implementation for DisplayPort link-training tunable PHY repeaters (LTTPRs). The device includes an upstream facing port to interface with an external DisplayPort source device and a downstream facing port to interface with an external DisplayPort sink device and the upstream facing port. The upstream facing port is configured to perform operations including receiving a main link data stream from an external transmitting display device, generating an outbound main link data stream, and providing the outbound main link data stream for transmitting by the external device. The device is also configured for receiving an updated main link data stream corresponding to the outbound main link data stream and sending the updated main link data stream to the downstream facing port to be transmitted to a receiving display device.

Abstract: Apparatuses, systems, and methods for hierarchical memory systems are described. A hierarchical memory system can leverage persistent memory to store data that is generally stored in a non-persistent memory, thereby increasing an amount of storage space allocated to a computing system at a lower cost than approaches that rely solely on non-persistent memory. In an example apparatus, an input/output (I/O) device can receive signaling that includes a command to write to or read data from an address corresponding to a non-persistent memory device, and can determine where to redirect the request. For example, the I/O device can determine to write or read data to and/or from the non-persistent memory device or the persistent memory device based at least in part on one or more characteristics of the data.

Abstract: Techniques in electronic systems, such as in systems comprising a CPU die and one or more external mixed-mode (analog) chips, may provide improvements advantages in one or more of system design, performance, cost, efficiency and programmability. In one embodiment, the CPU die comprises at least one microcontroller CPU and circuitry enabling the at least one CPU to have a full and transparent connectivity to an analog chip as if they are designed as a single chip microcontroller, while the interface design between the two is extremely efficient and with limited in number of wires, yet may provide improved performance without impact to functionality or the software model.

Abstract: Methods, apparatus, and computer platforms and architectures employing many-to-many and many-to-one peripheral switches. The methods and apparatus may be implemented on computer platforms having multiple nodes, such as those employing a Non-uniform Memory Access (NUMA) architecture, wherein each node comprises a plurality of components including a processor having at least one level of memory cache and being operatively coupled to system memory and operatively coupled to a many-to-many peripheral switch that includes a plurality of downstream ports to which NICs and/or peripheral expansion slots are operatively coupled, or a many-to-one switch that enables a peripheral device to be shared by multiple nodes. During operation, packets are received at the NICs and DMA memory writes are initiated using memory write transactions identifying a destination memory address.

Abstract: A method by a network device for dynamically detecting emotional states of a user operating a client end station to interact with an application. The method includes receiving information regarding user inputs received by the client end station from the user while the user interacted with the application during a particular time period and determining an emotional state of the user based on analyzing the information and information regarding user inputs received by the client end station from the user while the user interacted with the application during one or more previous time periods that together with the particular time period form a time window.

Abstract: Aspects of the present disclosure relate to an interconnect comprising interfaces to communicate with respective requester and receiver node devices, and home nodes. Each home node is configured to: receive requests from one or more requester nodes, each request comprising a target address corresponding to a target receiver nodes; and transmit each said request to the corresponding target receiver node. Mapping circuitry is configured to: associate each of said plurality of home nodes with a given home node cluster; perform a first hashing of the target address of a given request, to determine a target cluster; perform a second hashing of the target address, to determine a target home node within said target cluster; and direct the given message, to the target home node.

Abstract: A method for delivering multiple write commands is provided. The method includes: encoding data to be written and corresponding addresses in the multiple write commands to obtain encoded data and an encoded address, wherein the addresses are not sequential; generating a virtual burst write command according to the encoded data and the encoded addresses; and transmitting a virtual burst-mode start indicator and the virtual burst write command through a serial bus.

Abstract: One embodiment is directed to a multi-rack rack controller for an automated infrastructure management (AIM) system comprising a plurality of independent patching equipment bus interfaces. Another embodiment is directed to a rack controller comprising at least one rack controller interface configured to connect the rack controller to another rack controller. Each rack controller interface comprises a respective termination circuit. The rack controller is configured to determine whether each rack controller interface is connected to another rack controller as a function of a respective sense signal developed by the termination circuit associated with said rack controller interface. Another embodiment is directed to a rack controller comprising a base unit having a locate button disposed on the front of the base unit. Other embodiments are disclosed.

Abstract: In embodiments of the present disclosure, there is provided a solution for managing a USB connection between a USB device and a host device. According to embodiments of the present disclosure, a USB management server receives, from a USB management client at a host device, USB ID information for identifying a USB device that is plugged into the host device. Whether the USB ID information is valid is determined based on an authentication policy for authenticating the USB device. If the USB ID information is valid, the USB management client is instructed to permit a connection between the USB device and the host device. Accordingly, the connection may be managed by the USB management server. Embodiments of the present disclosure present an effective way for managing USB connections in a centralized way, which provides various flexible authentication policies and requires less manual operations.

Abstract: A shared memory provides multi-channel access from multiple computing or host devices. A priority circuit prioritizes the multiple memory requests that are submitted as bids from the multiple host channels, such that those memory access requests that do not give rise to a conflict may proceed in parallel. The shared memory may be multi-ported and a routing circuit routes the prioritized memory access request to the appropriate memory ports where the allowed memory access requests may be carried out.

Abstract: Switch topology-aware path selection in an information processing system is provided. For example, an apparatus comprises a host device comprising a processor coupled to a memory. The host device is configured to communicate with a storage system over a network with a plurality of switches. The host device is further configured to obtain topology information associated with the plurality of switches in the network, and select a path from the host device to the storage system through one or more of the plurality of switches based at least in part on the obtained topology information.

Abstract: A semiconductor storage device includes a bridge chip and memory chips connected to the bridge chip by a plurality of channels. The bridge chip includes a first delay circuit for setting the start of a first timing signal for a first memory chip output via a first channel and a second delay circuit for setting the start of for second timing signal for a second memory chip output via a second channel. A controller on the bridge chip controls at least one of the first and second delay circuits to adjust the start time of at least one of the first and second timing signals such that data sequences from the first and second memory chips will be aligned in time. The controller combines the data sequence from the first memory chip with the data sequence from the second memory chip to generate an interleaved serial sequence.

Abstract: A memory chip may include: a plurality of memory banks; a data storage configured to store access information indicative of access operations for one or more segments of the plurality of memory banks; and a refresh controller configured to perform a refresh operation of the one or more segments based, at least in part, on the stored access information.

Abstract: Certain aspects of the present disclosure provide a method for performing parallel data processing, including: receiving data for parallel processing from a data processing requestor; generating a plurality of data sub-blocks; determining a plurality of data portions in each data sub-block of the plurality of data sub-blocks; changing an order of the plurality of data portions in at least one data sub-block of the plurality of data sub-blocks; providing the plurality of data sub-blocks, including the at least one data sub-block comprising the changed order of the plurality of data portions, to a plurality of processing units for parallel processing; and receiving processed data associated with the plurality of data sub-blocks from the plurality of processing units.

Abstract: Techniques in electronic systems, such as in systems comprising a CPU die and one or more external mixed-mode (analog) chips, may provide improvements advantages in one or more of system design, performance, cost, efficiency and programmability. In one embodiment, the CPU die comprises at least one microcontroller CPU and circuitry enabling the at least one CPU to have a full and transparent connectivity to an analog chip as if they are designed as a single chip microcontroller, while the interface design between the two is extremely efficient and with limited in number of wires, yet may provide improved performance without impact to functionality or the software model.

Abstract: A system that includes a first die with a central processing unit (CPU) and a second die electrically coupled to the first die by die-to-die interconnects is described. During operation, the first die: provides, to the second die, a set of predefined wake-up events; provides, to the second die, a message that transitions power-management control of the first die to the second die; and transitions the first die from a first operating mode to a second operating mode that has lower power consumption than that of the first operating mode. Then, the second die: determines an occurrence of a predefined wake-up event based at least in part on the set of predefined wake-up events; and provides, to the first die, information that initiates a transition of the first die from the second operating mode to the first operating mode.

Abstract: Techniques in electronic systems, such as in systems comprising a CPU die and one or more external mixed-mode (analog) chips, may provide improvements advantages in one or more of system design, performance, cost, efficiency and programmability. In one embodiment, the CPU die comprises at least one microcontroller CPU and circuitry enabling the at least one CPU to have a full and transparent connectivity to an analog chip as if they are designed as a single chip microcontroller, while the interface design between the two is extremely efficient and with limited in number of wires, yet may provide improved performance without impact to functionality or the software model.

Abstract: Described are mechanisms and methods to facilitate power saving in Type-C connectors. Some embodiments may comprise an interface to a Configuration Channel (CC) signal path and to a ground signal path of a Universal Serial Bus (USB) Type-C connector port, a first circuitry, and a second circuitry. The first circuitry may be operable to place toggled values on the CC signal path. The second circuitry may be operable to couple the ground signal path to a detection signal path. The placement of the toggled values on the CC signal path is enabled when the detection signal path carries a first value that corresponds with the USB Type-C connector port being connected to a USB Type-C device, and may be disabled when the detection signal path carries a second value that corresponds with the USB Type-C connector port not being connected to a USB Type-C device.

Abstract: A calibration device includes a main control unit, an interface conversion unit and an electronic load generation unit. The electronic load generation unit provides an electronic load, so that a USB control chip generates a constant load current. The USB control chip uses at least one preset conversion parameter to generate an analog-to-digital conversion value according to the constant load current. The main control unit generates a to-be-calibrated output current according to the analog-to-digital conversion value. The main control unit generates at least one calibrated conversion parameter according to the constant load current and the to-be-calibrated output current. The USB control chip uses the at least one calibrated conversion parameter to generate a calibrated analog-to-digital conversion value, so that an over current protection mechanism is accurately enabled.

Abstract: A communication control device, includes a memory; and a processor coupled to the memory and the processor configured to: store, in the memory, instructions of standby processing in a specific processing order, when a network coupling is being established to perform communication, acquire a specific instructions, update, in the memory, the instructions of standby processing based on a type of the specific instructions, a type of the instructions of standby processing and a relationship specified by order in which the specific instructions are acquired, and after an establishment of the network coupling is completed, perform the instructions of standby processing in a specific processing order.