Patents Examined by Deven Collins
  • Patent number: 6103547
    Abstract: Devices and methods for reducing lead inductance in integrated circuit (IC) packages. More specifically to an integrated circuit package configuration for high speed applications where the inductance of the leads is reduced or minimized in high capacity semiconductor device packages. The integrated circuit package assembly comprises a substrate, semiconductor device, insulating covering or coating, if desired, a semiconductor device retainer, lead frame, and wire bond interconnections.
    Type: Grant
    Filed: January 17, 1997
    Date of Patent: August 15, 2000
    Assignee: Micron Technology, Inc.
    Inventors: David J. Corisis, Brent Keeth
  • Patent number: 6080604
    Abstract: A semiconductor device having a semiconductor chip and a TAB lead adhering to a surface of the semiconductor chip by a TAB tape which electrically connects an internal terminal arranged in a center part of a surface of the semiconductor chip to an external terminal arranged around a periphery of the semiconductor chip. One embodiment according to the present invention is an LCO semiconductor device having the TAB lead connecting to a lead-frame assembled in an IC package. Another embodiment according to the present invention is a TAB tape of thermo-plasticity comprising a first surface having a first softening temperature and a second surface having a second softening temperature which is different from the first softening temperature.
    Type: Grant
    Filed: July 29, 1997
    Date of Patent: June 27, 2000
    Assignee: Fujitsu Limited
    Inventor: Masaki Waki
  • Patent number: 6020252
    Abstract: A thin layer of semiconductor material is produced by implanting ions through a flat face of a semiconductor wafer in order to create a layer of microcavities, the ion dose being within a specific range in order to avoid the formation of blisters on the flat face. The resulting wafer is then subjected to a thermal treatment step in order to achieve coalescence of the microcavities. During or following the thermal treatment, a thin layer is separated from the rest of the wafer by application of mechanical force.
    Type: Grant
    Filed: May 14, 1997
    Date of Patent: February 1, 2000
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Bernard Aspar, Michel Bruel, Thierry Poumeyrol
  • Patent number: 6013536
    Abstract: Disclosed is a method for automating support pillar design in air dielectric interconnect structures. The method includes selecting features having an interconnect dimension from a first mask. Providing an intermediate support pattern defining a pillar spacing. Identifying overlap regions where the features selected from the first mask overlap the intermediate support pattern. The method further including filtering the overlap regions to eliminate features that are less than the interconnect dimension. The filtering being configured to define discrete pillar locations associated with the first mask.
    Type: Grant
    Filed: April 22, 1997
    Date of Patent: January 11, 2000
    Assignee: VLSI Technology, Inc.
    Inventors: Edward D. Nowak, Subhas Bothra
  • Patent number: 5989991
    Abstract: An insulating layer having an irregular upper surface is provided to improve the adhesion and increase the coefficient of friction between the insulating layer and a bonding pad formed over the insulating layer. By making the upper surface of the insulating layer irregular, the area of contact between the bonding pad and the insulating layer is increased. As a result, the adhesion between the bonding pad and the insulating layer is also increased. This prevents the bonding pad from being detached from the insulating layer when a bonding wire is later attached to the bonding pad. The upper surface of the insulating layer can be made irregular by etching one or more cavities in the upper surface of the insulating layer. The upper surface of the insulating layer can alternatively be made irregular by forming one or more raised structures beneath the insulating layer. The raised structures cause plateaus to be formed at the upper surface of the insulating layer.
    Type: Grant
    Filed: June 20, 1997
    Date of Patent: November 23, 1999
    Assignee: Integrated Device Technology, Inc.
    Inventor: Chuen-Der Lien
  • Patent number: 5985699
    Abstract: Cells in which clock skew or variation in transistor properties is to be suppressed are specified and inputted. Next, a method of checking unoccupied cells for arranging dummy cells is specified and inputted. Next, a step of allowing a CAD tool to recognize the unoccupied cells is carried out. In this step, a check is made over a chip so as to see an area in which the cells are not located and to recognize this area as the unoccupied cells. Then, the step of checking whether or not the unoccupied cells are present near the cells to be processed is carried out. In this step, for the cells to be processed, the unoccupied cells are checked by the specified method of checking the unoccupied cells. Then, the dummy cells are arranged in the unoccupied cells.
    Type: Grant
    Filed: June 9, 1998
    Date of Patent: November 16, 1999
    Assignee: NEC Corporation
    Inventor: Katsuhiko Yokoyama
  • Patent number: 5976914
    Abstract: In accordance with the invention, integrated circuit dies may be packaged in a plastic package employing an area area array technology such as a conductive ball grid array, column grid array or pin grid array. One aspect of the invention is an integrated circuit package (10) which includes an electronic circuit enclosed by a plastic body (12, 14). The molded plastic body has a first major surface opposing a second major surface. The first major surface of integrated circuit (10) has a plurality of openings therein. One of a plurality of conductive pads (18) is adjacent to each one of the openings and is electrically connected to the electronic circuit. Each of a plurality of conductors (20) is electrically connected to one of the pads (18) and protrudes from one of the openings (22).
    Type: Grant
    Filed: August 26, 1997
    Date of Patent: November 2, 1999
    Assignee: Texas Instruments Incorporated
    Inventors: John H. Abbott, Navinchandra Kalidas, Raymond W. Thompson
  • Patent number: 5976975
    Abstract: Capping a low resistivity metal conductor line or via with a refractory metal allows for effectively using chemical-mechanical polishing techniques because the-hard, reduced wear, properties of the refractory metal do not scratch, corrode, or smear during chemical-mechanical polishing. Superior conductive lines and vias are created using a combination of both physical vapor deposition (e.g., evaporation or collimated sputtering) of a low resistivity metal or alloy followed by chemical vapor deposition (CVD) of a refractory metal and subsequent planarization. Altering a ratio of SiH.sub.4 to WF.sub.6 during application of the refractory metal cap by CVD allows for controlled incorporation of silicon into the tungsten capping layer. Collimated sputtering allows for creating a refractory metal liner in an opening in a dielectric which is suitable as a diffusion barrier to copper based metalizations as well as CVD tungsten.
    Type: Grant
    Filed: July 10, 1998
    Date of Patent: November 2, 1999
    Assignee: International Business Machines Corporation
    Inventors: Rajiv V. Joshi, Jerome J. Cuomo, Hormazdyar M. Dalal, Louis L. Hsu
  • Patent number: 5966630
    Abstract: A wire bonding method in which an electric spark is generated between a lower end of a wire inserted through a capillary tool and a torch so as to form a small diameter ball, and then the electric spark is again generated so as to increase the diameter of the ball to form a large ball. The large ball is pressed against a pad on a chip with a lower surface of the capillary tool, so that the large ball is bonded to the pad. Since the large ball is soft, it can be sufficiently crushed by the lower surface of the capillary tool and be tightly bonded to the pad. Accordingly, the method accomplishes excellent wire bonding immediately after a bonding operation is restarted even after a long waiting time between bonding operations.
    Type: Grant
    Filed: April 24, 1998
    Date of Patent: October 12, 1999
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Takayuki Yoshiyama
  • Patent number: 5963794
    Abstract: An offset die stacking arrangement having at least one upper level die having a width which is less than the distance separating the opposing bonding sites of the underlying die. The upper die is suspended above the lower die on one or more pillars and rotated within a plane parallel to the lower die through an angle which insures that none of the bonding sites of the lower die are obstructed by the upper die. Once the dice are fixed in this manner, the entire assembly is subjected to the wire bonding process with all of the bonds being made in the same step.
    Type: Grant
    Filed: February 24, 1998
    Date of Patent: October 5, 1999
    Assignee: Micron Technology, Inc.
    Inventors: Rich Fogal, Michael B. Ball
  • Patent number: 5963793
    Abstract: Microelectronic packages are formed wherein solder bumps on one or more substrates are expanded, to thereby extend and contact the second substrate and form a solder connection. The solder bumps are preferably expanded by reflowing additional solder into the plurality of solder bumps. The additional solder may be reflowed from an elongated, narrow solder-containing region adjacent the solder bump, into the solder bump. After reflow, the solder bump which extends across a pair of adjacent substrates forms an arched solder column or partial ring of solder between the two substrates.
    Type: Grant
    Filed: June 12, 1998
    Date of Patent: October 5, 1999
    Assignee: MCNC
    Inventors: Glenn A. Rinne, Philip A. Deane
  • Patent number: 5960308
    Abstract: A process for making a chip sized semiconductor device, in which a semiconductor chip is prepared so as to have electrodes on one of surfaces thereof and an electrically insulating passivation film formed on the one surface except for areas where the electrodes exist. An insulation sheet is prepared so as to have first and second surfaces and a metallic film coated on the first surface. The second surface of the insulation sheet is adhered on the one surface of the semiconductor chip. First via-holes are provided in the metallic film at positions corresponding to the electrodes. Second via-holes are provided in the insulation sheet at positions corresponding to the first via-holes so that the electrodes are exposed. The metallic film is electrically connected to the electrodes of the semiconductor chip through the first and second via-holes. A circuit pattern is formed from the metallic film so that the circuit pattern has external terminal connecting portions.
    Type: Grant
    Filed: March 18, 1998
    Date of Patent: September 28, 1999
    Assignee: Shinko Electric Industries Co. Ltd.
    Inventors: Masatoshi Akagawa, Mitsutoshi Higashi, Hajime Iizuka, Takehiko Arai
  • Patent number: 5960253
    Abstract: A method of manufacturing a semiconductor memory device includes a first step of forming a plurality of memory cells with a redundancy portion through fine patterning, a second step of searching a defect in masks used in the fine patterning and a third step of forming offset via holes so as to interconnect the redundancy portion instead of a defective portion identified by an inspection in non-fine patterning conducted after the fine patterning.
    Type: Grant
    Filed: July 24, 1997
    Date of Patent: September 28, 1999
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Takeshi Fujino
  • Patent number: 5956601
    Abstract: A method of manufacturing a semiconductor device mountable in a module supporter. According to the present invention, a semiconductor substrate has a plurality of semiconductor modules, where each semiconductor module has a semiconductor chip covered with a protective material, such as resin, on a first surface and a connector formed on a second surface which is electrically connected to the semiconductor chip. An adhesive layer is applied to the first surface of the substrate. The adhesive layer has a plurality of opening portions arranged to positionally correspond to the plurality of semiconductor modules on the substrate. The substrate and the adhesive layer are cut into individual substrates each having the semiconductor chip so that each semiconductor module has the adhesive layer on a periphery of the protective material. Individual substrates containing a semiconductor module are bonded to the supporter having a concave portion for holding the semiconductor module.
    Type: Grant
    Filed: April 17, 1997
    Date of Patent: September 21, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Sumie Sato, Jun Ohmori
  • Patent number: 5956606
    Abstract: An electrical interconnect structure, including a first component (300), a second component (320), and an electrical interconnect electrically and mechanically interconnecting the first component to the second component, the electrical interconnect including a first solder sphere (314) and a second solder sphere (318) stacked on each other. A semiconductor die (200, 100) that is bumped and packaged utilizing the electrical interconnect structure is also disclosed.
    Type: Grant
    Filed: October 31, 1997
    Date of Patent: September 21, 1999
    Assignee: Motorola, Inc.
    Inventor: Terry Burnette
  • Patent number: 5956575
    Abstract: Microconnectors are described that can be fabricated on circuitry, the microconnectors for physically and/or electrically connecting separate structures. The microconnectors permit partitioning of a function among a plurality of chips. The microconnectors include a latching member.
    Type: Grant
    Filed: May 21, 1998
    Date of Patent: September 21, 1999
    Assignee: International Business Machines Corporation
    Inventors: Claude Louis Bertin, John Edward Cronin
  • Patent number: 5953589
    Abstract: A ball grid array semiconductor package using a flexible circuit board, in which the flexible circuit board has no conductive via hole nor solder mask while having a thin structure formed at only one surface thereof with a circuit pattern having a small length. The flexible circuit board is mounted with a metallic carrier frame to achieve an easy handling thereof, a reduction in the inductance, impedance and coupling effect of adjacent circuit patterns and an easy discharge of heat from a semiconductor chip, thereby achieving an improvement in electrical performance and an improvement in heat discharge performance. The metallic carrier frame has a plurality of openings adapted to increase the bonding force between an encapsulate and constituting elements of the package, thereby removing a bending phenomenon of the package, and a method for fabricating such a BGA semiconductor package. The invention also provides a method for fabricating such a BGA semiconductor package.
    Type: Grant
    Filed: August 20, 1997
    Date of Patent: September 14, 1999
    Assignees: Anam Semiconductor Inc., Amkor Technology, Inc.
    Inventors: Il Kwon Shim, Young Wook Heo, Robert Francis Darreaux
  • Patent number: 5950072
    Abstract: An integrated circuit package had leadless solderballs attached to the substrate with a conductive thermoplastic adhesive. The leadless solderballs are preferably made with a copper-nickel-gold alloy. The conductive thermoplastic is preferably of the silver fill type. The integrated circuit package is placed in a frame and held to the printed circuit board with a clamp or with a screw.
    Type: Grant
    Filed: July 25, 1997
    Date of Patent: September 7, 1999
    Assignee: STMicroelectronics, Inc.
    Inventor: Daniel G. Queyssac
  • Patent number: 5946554
    Abstract: In a method of producing a resin-sealed electronic device, a solder resist layer including a silicone family surfactant is coated on a printed circuit board. Thereafter, an electronic component is mounted on the solder resist layer through adhesives, and is sealed by sealing resin. The content of the silicone family surfactant in the solder resist layer is less than 3 wt %, more preferably, is in a range of 0.2 wt % to 1 wt %. Accordingly, adhering reliability of the sealing resin relative to the solder resist can be improved, thereby resulting in high reliability of the resin-sealed electronic device for a long time.
    Type: Grant
    Filed: May 27, 1997
    Date of Patent: August 31, 1999
    Assignee: Denso Corporation
    Inventors: Masashi Echigo, Hiroyuki Yamakawa
  • Patent number: 5946590
    Abstract: A bump is formed on a semiconductor wafer which has a pad electrode thereon. The method includes the steps for coating a first organic film on a semiconductor water; drying the first organic film; applying an excimer laser to a portion of the first organic film substantially corresponding to the pad electrode to thereby form a first opening in the organic film; forming at least one metallic film on the first organic film and the opening; coating a second organic film on the metallic film; drying the second organic film; applying an excimer laser to a portion of the second organic film substantially corresponding to the first opening to thereby form a second opening in the second organic film; and providing and melting solder at the second opening to form a solder bump. Since the openings of the organic films are formed by the excimer laser, the openings can be formed in a short time with high accuracy. Thus, the bump with high quality can be formed at a low cost.
    Type: Grant
    Filed: December 9, 1997
    Date of Patent: August 31, 1999
    Assignee: Citizen Watch Co., Ltd.
    Inventor: Tetsuo Satoh