Abstract: Two kinds of metal patterns 12, 13 are formed on a semiconductor wafer 11 to deposit a surface protective film 14 on the entirety of the surface to implement patterning to the surface protective film 14 so that the surface of the metal pattern 12 at least on dicing lines of the metal patterns 12, 13 is exposed to deposit barrier metal 15 on the entirety of the surface to remove, by etching, at the same time, portions on the dicing lines of the barrier metal 15 and the metal pattern 12 on the dicing lines of the metal patterns 12, 13 to carry out dicing with respect to the semiconductor wafer 11 along the dicing lines from which the metal pattern 12 has been removed to thereby prevent that the end portion of the metal pattern turned up by dicing comes into contact with inner lead or bonding wire so that any failure takes place.

Abstract: A semiconductor package includes a substrate having one or more dice mounted thereto, and a cover adapted to protect and form a sealed space for the dice. The cover can be pre-fabricated of molded plastic, or stamped metal, and attached to the substrate using a cured seal. A hole can also be provided through the substrate to permit pressure equalization during formation of the seal. The cover can be prefabricated in an enclosed configuration for attachment directly to the substrate, or in a planar configuration for attachment to a peripheral ridge on the substrate. In either embodiment, the cover is removable to permit defective dice to be replaced or repaired.

Abstract: A method and encapsulation material for encapsulating the solder joints of an IC device mounted on the substrate of an electronic circuit assembly. The encapsulation material is formulated to be sufficiently opaque to x-radiation to enable the use of x-radiation imaging techniques to detect air pockets and voids in the encapsulation material that might degrade the fatigue life properties of the solder joints encapsulated by the encapsulation material. For the purpose of enhancing the fatigue life properties of the solder joints, the encapsulation material contains a filler material dispersed in a polymeric material, such as an epoxy, such that the encapsulation material is characterized by a coefficient of thermal expansion approximately equal to that of the solder joints. The filler material contains a sufficient amount of an element to render the encapsulation material opaque to x-radiation.

Abstract: A method for forming a solder bump pad (22), and more particularly converting a wire bond pad (12) of a surface-mount IC device (10) to a flip chip solder bump pad (22), such that the IC device (10) can be flip-chip mounted to a substrate. The process generally entails an aluminum wire bond pad (12) on a substrate, with at least a portion of the wire bond pad (12) being exposed through a dielectric layer (16) on the substrate. A nickel layer (24) is then deposited on the portion of the wire bond pad (12) exposed through the dielectric layer (16). The nickel layer (24) is selectively deposited on the exposed portion of the wire bond pad (12) without use of a masking operation, such as by an electroless deposition technique. The nickel layer (24) completely overlies the aluminum wire bond pad (12), and therefore protects the bond pad (12) from oxidation due to exposure. Thereafter, the solder bump pad (22) is formed by depositing a solderable material on the nickel layer (24).

Abstract: A lead frame having protection against electrostatic discharge is disclosed. The lead frame having protection against electrostatic discharge includes a multiplicity of leads and an electrostatic discharge protection device. The electrostatic discharge protection device includes a conductive layer and a protection layer. The protection layer is arranged to contact a plurality of leads and is formed from an electrostatic discharge protection material, which insulates the leads from the conductive layer at voltages below a predefined threshold voltage and establishes an electrical connection between the leads and the conductive layer at voltages above the threshold voltage.

Abstract: The present invention is a method of providing a protective covering on an electronic package including a first circuitized substrate, a semiconductor chip positioned on and electrically coupled to the first substrate, and a plurality of conductors also on the substrate for electrically connecting the substrate to an external circuitized substrate. In one version, the method comprises covering substantially all of the external surfaces of the substrate, the semiconductor chip and a portion of the plurality of conductors with a protective covering from immersion in a dielectric solution (e.g., TEFLON AF). The coatings can also be applied by brushing, spraying, or chemical vapor deposition. In an alternative embodiment, all of the external surfaces, including all of the conductors, are coated with the protective covering (e.g., to facilitate package shipment or other handling). The resulting electronic packages are also described herein.

Abstract: Martensitic or austenitic structural-hardening conductive alloy connection leads. Electronic component and fabrication process.

Abstract: An electronic package is fabricated by providing a thin, circuitized substrate having electrical circuitry on a first surface; and then molding a dielectric body to the first surface of the substrate. The dielectric body contains an opening for exposing a portion of the surface of the thin circuitized substrate having at least a portion of the electrical circuitry. A semiconductor device is then positioned within the opening of the molded dielectric body and is electrically coupled to at least a portion of the electrical circuitry on the exposed portion of the surface of the thin circuitized substrate. Next, a plurality of electrical conductive members are secured to a surface of the thin circuitized substrate that is opposite the first surface.

Abstract: An integrated circuit package having a die supported on a ball grid array substrate and wire bonds electrically connecting the die to the substrate. Supported on the substrate is a lock ring having a threaded opening encircling the die. Encapsulant covers the die and the wire bonds and adheres the lock ring to the substrate. A heat sink having a threaded portion can be threaded into the lock ring into an operative cooling position relative to the die and subsequently to an unthreaded removed position. When in the latter position, a repair station can be positioned over the package and the solder balls are accessible for hot gas melting thereof for removal (or replacement) of the package from the underlying motherboard.

Abstract: There is disclosed herein a method for adhering metallizations to a substrate, comprising the steps of: (1) providing a substrate having a first surface; (2) applying a coating atop the first surface, such that the coating has a second surface bonded to the first surface, and a third surface generally conforming with the second surface; (3) etching away material from the third surface, so as to roughen and form pits in the third surface; and (4) attaching a metallization to the pits in the third surface by plating, sputtering, or similar means.

Abstract: An Al electrode pad and a photoresist pattern having an opening portion on the Al electrode pad on a semiconductor substrate on which a surface protective film has been formed are formed. Then, a barrier metal layer is formed on the whole substrate surface, and a resist film and the barrier metal layer on the resist film are removed by lift-off, thus forming a solder bump foundation layer. Furthermore, an adhesive tape is stuck to the substrate surface and then the adhesive tape is peeled off, thereby to perform a residue removing process for removing resist film residues and useless barrier metal residues other than the solder bump foundation layer. With this, it is possible to further remove residues that have remained on the substrate surface without being lifted off and caused a defective device with an adhesive tape, thus making it possible to form a solder bump of high reliability in flip chip bonding.

Abstract: A method of processing a semiconductive material wafer includes, a) providing a semiconductive material wafer having integrated circuitry fabricated within discrete die areas on the wafer, the discrete die areas having bond pads formed therewithin; b) cutting at least partially into the semiconductive material wafer about the die areas to form a series of die cuts, the cuts having edges; c) depositing an insulative material over the wafer and to within the cuts to at least partially cover the cut edges and to at least partially fill the cuts with the insulative material; d) removing the insulative material from being received over the bond pads and leaving the insulative material within the die cuts; and e) after the removing, cutting into and through the insulative material within the die cuts and through the wafer. A semiconductor chip includes an outer surface having conductive bond pads proximately associated therewith. Side edges extend from the outer surface.