Abstract: A method of manufacturing a bonding substrate is disclosed. An oxide film is formed on the surface of at least one of two semiconductor substrates, and the two substrates are brought into close contact with each other via the oxide film. The substrates are heat-treated in an oxidizing atmosphere in order to firmly join the substrates together. Subsequently, an unjoined portion at the periphery of a device-fabricating substrate is completely removed, and the thickness of the device-fabricating substrate is reduced to a desired thickness so as to yield a thin film. The surface of the thin film is then etched through vapor-phase etching in order to make the thickness of the thin film uniform. In the method, the oxide film on the unjoined portion of at least the support substrate is removed before the surface of the thin film is subjected to vapor-phase etching.

Abstract: A method of making a multiple part compliant interface for a microelectronic package including the steps of providing a first microelectronic element having electrically conductive parts, providing an array of curable elastomer support pads in contact with the first microelectronic element, curing the curable elastomer support pads while the support pads remain in contact with the first microelectronic element and providing an array of adhesive pads in contact with the support pads, whereby each adhesive pad is disposed over and in substantial alignment with one of the support pads. A second microelectronic element having electrically conductive parts is then assembled in contact with the array of adhesive pads by abutting the second microelectronic element against the array of adhesive pads and compressing the adhesive pads and support pads between the first and second microelectronic elements.

Abstract: A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 .mu.m in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.

Abstract: A semiconductor integrated circuit device, and method of manufacturing the same, having a conventional-type lead frame with the die paddle removed. In particular, the die paddle is replaced with a section of tape that is supported by the ends of the lead fingers. The semiconductor die is attached to the tape so that it may be wire bonded to the lead fingers. The tape contains at least one slot to allow for expansion and/or contraction of the tape due to various temperatures experienced during the manufacturing process so that the tape does not wrinkle or warp to alter the position of the die.

Abstract: A wafer level hermetically packaged integrated circuit has a protective cover wafer bonded to a semiconductor device substrate wafer. The substrate wafer may contain a cavity. The cover wafer seals integrated circuits and other devices including but not limited to air bridge structures, resonant beams, surface acoustic wave (SAW) devices, trimmable resistors, and micromachines. Some devices, such as SAWs, are formed on the surface of cavities formed in the protective cover wafer. Die are separated to complete the process.

Abstract: A method for producing a plastic material composite component and a corresponding component are disclosed. The component is typically a smart card having a semiconductor chip embedded in plastic material. The component is provided with a contact area on an outer component surface. Electrical interconnection between the contact area and the chip is effected during injection molding the component.

Abstract: A method and apparatus that provides process monitoring within a semiconductor wafer processing system using multiple process parameters. Specifically, the apparatus analyzes multiple process parameters and statistically correlates these parameters to detect a change in process characteristics such that the endpoint of an etch process may be accurately detected, as well as detecting other characteristics within the chamber. The multiple parameters may include optical emissia, environmental parameters such as pressure and temperature within the reaction chamber, RF power parameters such as reflected power or tuning voltage, and system parameters such as particular system configurations and control voltages.

Abstract: A semiconductor device package containing a semiconductor die uses a platform mounted on an active face of the die. The platform electrically connects to at least one bond pad on the die. A package lid electrically connects to the platform on the die and a package case connection. The package case connection is also electrically connected to at least one external connector on the package. The platform and package lid thereby connect the at least one bond pad on the die to the at least one external connector on the package. Using the platform and lid for electrical connections from the semiconductor die bond pads to the external package connector reduce the number of bond fingers required to surround the perimeter of the die. The package lid and platform may, for example, be used for ground or power connections to the die bond pads.

Abstract: The disclosure relates to a mass memory with very large-scale integration as well as to a method for the manufacture of such a memory.

Abstract: Nickel films 22, 25 are formed on copper pads 21, 24 on a substrate 11, and gold layers 23, 26 are further formed on the nickel films 22, 25. To suppress formation of compound of gold and tin which spoils reliability of soldering, formation of gold layers 23, 26 on the nickel films 22, 25 is effected by very thin substitutional plating method. As a result, a solder bump 17 is formed favorably. Besides, an nickel oxide film 32 formed on the surface of the gold layer 23 is removed by plasma etching. As a result, bonding of wire 15 is also excellent.

Abstract: Disclosed is a semiconductor wafer, and the method of making the same, the wafer being formed to have a multiplicity of raised contact pads on its surface. The contact pads are formed with conductors which are disposed on the surface of the wafer and which are coupled to internal circuitry embedded in the wafer rough vias in the wafers surface. The contact pads are in a raised elevational relationship relative to the surface conductors. After the wafer is fully processed, by dicing individual integrated circuit chips out of the wafer, each chip can then be mounted on a higher level of assembly, such as a printed circuit board. The raised contact pads originally formed on the wafer, and therefore formed on each individual chip, provide the contact points by which the chip can be bonded with matingly arranged contact pads on the higher level of assembly.

Abstract: A method of making a multiple 3-dimensional semiconductor device substrate includes the steps of providing a plurality of devices each device including a semiconductor die and having a reference face requiring a subsequent face processing. The reference face of each of the plurality of devices is positioned upon a planar reference surface. The planar reference surface corresponds to a release layer having vacuum apertures disposed therein. The plurality of devices can be precisely aligned in a prescribed manner upon the release layer, wherein application of a vacuum source to the vacuum apertures holds the plurality of aligned devices at their respective reference faces upon the release layer. Molding compound is dispensed into gaps occurring between adjacent side faces of the plurality of devices other than the reference faces. Lastly, the molding compound is cured. A multiple 3-dimensional semiconductor device substrate is disclosed also.

Abstract: A method and apparatus for dicing semiconductor wafers is provided. The method comprises: forming an etch mask on the wafer, and then etching the wafer with a wet etchant, such as KOH, to form a peripheral groove around each die. Etching the wafer can be from the front side of the wafer, from the back side of the wafer or with partial etches from both sides. The etch process can be performed on a single wafer using a spray head apparatus or on batches of wafers using a recirculating dip tank apparatus.

Abstract: A method for packaging a semiconductor device (22) formed on a die (12) having opposing major surfaces includes pre-soldering the die (12) at wafer level using an electroplating process, wherein the die (12) has solder bumps disposed on each opposing major surface. The pre-soldered wafer (10) is then diced into pre-soldered dies. The die (12) is placed in a glass sleeve (45) and aligned with two bumpless lead assemblies (46, 48). The bumpless lead assemblies (46, 48) are solder bonded to the die (12) via a reflow process. The reflow process also partially melts the glass sleeve (45), thereby forming a hermetically sealed glass capsule (55) surrounding the semiconductor device (22).

Abstract: A packaging technique for electronic devices includes wafer fabrication of contacts that wrap down the inside surface of a substrate post. Inherently reliable contacts suitable for a variety of devices can be formed, via a simple fabrication process, with good wafer packing density. A trench is formed in the top surface of a substrate parallel to the edge of its electronic circuit. A gold beam wire extends from a connection point within the circuit into the trench. Unless an insulative substrate is used, the wire runs over an insulating layer that ends part way through the trench. After epoxy encapsulating the top of the substrate, it is back planed to form the bottom surface of the post. Then it is selectively back etched, to expose the bottom surface of the wire, to form the inside surface of the post, and to form the bottom surface of the finished device. A solderable lead wire runs from the exposed gold wire, down the inside surface of the post, and across its bottom.

Abstract: A lead-on-chip semiconductor device package is formed by attaching a lead frame having a single adhesive layer to a semiconductor chip. Electrode pads of the chip are electrically connected by bonding wires and mechanically connected by the adhesive layer to the lead frame, and then encapsulated by an encapsulant such as molding compound. The adhesive layer is formed from a liquid adhesive having a certain viscosity. The adhesive material is continuously applied to spaces between adjacent inner leads as well as the top surface of the leads and then cured. The leads are disposed at the same intervals and include some side leads with a larger width in order to form the adhesive layer with a uniform thickness. Thermoplastic resins are preferably used as the adhesive, but thermosetting resins may be used as well. In the case of thermoplastic resins, the temperature of a cure step is about 200.degree. C. and that of chip attachment step is about 400.degree. C.

Abstract: The specification describes a gettering technique for bonded wafers. The handle wafer is provided with a phosphorus predeposition to getter impurities from the handle wafer. The surface to be bonded of the handle wafer is then polished to prepare the wafer for bonding. During polishing the top side phosphorus layer is removed, thereby eliminating the potential for updiffusion of phosphorus from the gettering layer into the device regions of the device layer. The phosphorus gettering layer on the backside of the handle wafer is retained for additional gettering during the bonding operation and during subsequent processing of the device wafer.

Abstract: A hybrid lead frame having leads for conventional lead-to-I/O wire bonding, and leads for power and ground bussing that extend over a surface of the semiconductor die are provided where the leads for bussing are held in place by lead-lock tape to prevent bending and/or other movement of the bussing leads during manufacturing. More specifically, the lead-lock tape is transversely attached across a plurality of bussing leads proximate to and outside of the position where the die is to be attached.

Abstract: An organic light emitting device (10) is provided which is encapsulated by a Siloxane buffer layer (17.1). This Siloxane buffer layer (17.1) is applied to the diode (10) providing for protection against contamination, degradation, oxidation and the like. The Siloxane buffer layer (17.1) carries at least a second encapsulation layer (17.2).

Abstract: An external terminal fabrication method for a ball grid array (BGA) semiconductor package for directly forming a bump on a substrate includes the steps of forming a plurality of conductive islands spaced from each other on an upper surface of a substrate, forming a photoresist film on the substrate, exposing the respective islands through the photoresist film, forming a conductive bump member on each of the exposed islands, and removing the photoresist film remaining on the substrate.