Abstract: One aspect of the invention relates to a power semiconductor device in lead frame technology and a method for producing the same. The power semiconductor device has a vertical current path through a power semiconductor chip. The power semiconductor chip has at least one large-area electrode on its top side and a large-area electrode on its rear side. The rear side electrode is surface-mounted on a lead frame chip island of a lead frame and the top side electrode is electrically connected to an internal lead of the lead frame via a connecting element. The connecting element has an electrically conductive film on a surface facing the top side electrode, the electrically conductive film extending from the top side electrode to the internal lead.

Abstract: A light emitting device having a light extraction structure, which is capable of achieving an enhancement in light extraction efficiency and reliability, and a method for manufacturing the same. The light emitting device includes a semiconductor layer having a multi-layered structure including a light emission layer; and a light extraction structure formed on the semiconductor layer in a pattern having unit structures. Further, the wall of each of the unit structures is sloped at an angle of ?45° to +45° from a virtual vertical line being parallel to a main light emitting direction of the light emitting device.

Abstract: A method of forming a metal ion transistor comprises forming a first electrode in a first isolation layer; forming a second isolation layer over the first isolation layer; forming a first cell region of a low dielectric constant (low-k) dielectric over the first electrode in the second isolation layer, the first cell region isolated from the second isolation layer; forming a cap layer over the second isolation layer and the first cell region, at least thinning the cap layer over the first cell region; depositing a layer of the low-k dielectric over the second isolation layer and the first cell region; forming metal ions in the low-k dielectric layer; patterning the low-k dielectric layer to form a second cell region; sealing the second cell region using a liner; and forming a second electrode contacting the second cell region and a third electrode contacting the second cell region.

Abstract: A semiconductor device includes an n-conductive type semiconductor substrate having a main side and a rear side, a p-conductive type layer arranged over the main side of the substrate, a main side n-conductive type region arranged in the p-conductive type layer, a rear side n-conductive type layer arranged over the rear side of the substrate, a first trench which reaches the substrate and penetrates the main side n-conductive type region and the p-conductive type layer, a second trench which reaches an inside of the p-conductive type layer, a second electrode layer, which is embedded in the second trench and connected to the p-conductive type layer. Hereby, the semiconductor device, in which the recovery property of a diode cell can be improved without damaging the property of a MOS transistor cell or an IGBT cell and the surge withstand property does not deteriorate, can be obtained.

Abstract: Semiconductor structures and methods of forming semiconductor structures, and more particularly to structures and methods of forming SiGe and/or SiGeC buried layers for SOI/SiGe devices. An integrated structure includes discontinuous, buried layers having alternating Si and SiGe or SiGeC regions. The structure further includes isolation structures at an interface between the Si and SiGe or SiGeC regions to reduce defects between the alternating regions. Devices are associated with the Si and SiGe or SiGeC regions.

Abstract: Described herein is a method of manufacturing a semiconductor device realizing higher performance by reducing contact resistance of an electrode. In the method, a gate insulating film, a gate electrode are formed on a semiconductor substrate. A first metal is deposited substrate, and a metal semiconductor compound layer is formed on the surface of the semiconductor substrate by making the first metal and the semiconductor substrate react each other by a first heat treatment. Ions having a mass equal to or larger than atomic weight of Si are implanted into the metal semiconductor compound layer. A second metal is deposited on the metal semiconductor compound layer. An interface layer is formed by making the second metal segregated at an interface between the metal semiconductor compound layer and the semiconductor substrate by diffusing the second metal through the metal semiconductor compound layer by a second heat treatment.

Abstract: A semiconductor light emitting device of the present invention includes a plurality of light emitting elements, a package body for storing the light emitting elements, wiring patterns being electrically connected to the light emitting elements, and Au wires for electrically connecting the light emitting elements and the wiring patterns, the package body including mounting concave portions for storing the respective light emitting elements, and storing concave portion for storing the mounting concave portions and the Au wires, the mounting concave portions being aligned on a linear line and spaced from each other with an equal pitch.

Abstract: A semiconductor power device supported on a semiconductor substrate that includes a plurality of transistor cells, each cell has a source and a drain region disposed on opposite sides of a gate region in the semiconductor substrate. A gate electrode is formed as an electrode layer on top of the gate region for controlling an electric current transmitted between the source and the drain regions. The gate electrode layer disposed on top of the semiconductor substrate is patterned into a wave-like shaped stripes for substantially increasing an electric current conduction area between the source and drain regions across the gate.

Abstract: A structure including a Si1-xGex substrate and a distributed Bragg reflector layer disposed directly onto the substrate. The distributed Bragg reflector layer includes a repeating pattern that includes at least one aluminum nitride layer and a second layer having the general formula AlyGa1-yN. Another aspect of the present invention is various devices including this structure. Another aspect of the present invention is directed to a method of forming such a structure comprising providing a Si1-xGex substrate and depositing a distributed Bragg reflector layer directly onto the substrate. Another aspect of the present invention is directed to a photodetector or photovoltaic cell device, including a Si1-xGex substrate device, a group III-nitride device and contacts to provide a conductive path for a current generated across at least one of the Si1-xGex substrate device and the group III-nitride device upon incident light.

Abstract: Provided are a wire structure, a method for fabricating a wire, a thin film transistor (TFT) substrate and a method for fabricating a TFT substrate. The wire structure includes a barrier layer formed on a substrate and including copper, copper solid solution layer.

Abstract: In one embodiment, a power integrated circuit device is provided. The power integrated circuit device includes a high-side power switch having a high voltage transistor and a low voltage transistor. The high voltage transistor has a gate, a source, and a drain, and is capable of withstanding a high voltage applied to its drain. The low voltage transistor has a gate, a source, and a drain, wherein the drain of the low voltage transistor is connected to the source of the high voltage transistor and the source of the low voltage transistor is connected to the gate of the high voltage transistor, and wherein a control signal is applied to the gate of the low voltage transistor from the power integrated circuit device.

Abstract: The present invention provides antifuse structures having an integrated heating element and methods of programming the same, the antifuse structures comprising first and second conductors and a dielectric layer formed between the conductors, where one or both of the conductors functions as both a conventional antifuse conductor and as a heating element for directly heating the antifuse dielectric layer during programming.

Abstract: The present invention is a method and an apparatus for optical modulation, for example for use in optical communications links. In one embodiment, an apparatus for optical modulation includes a first silicon layer having one or more trenches formed therein, a dielectric layer lining the first silicon layer, and a second silicon layer disposed on the dielectric layer and filling the trenches.

Abstract: It is an object of the present invention to form an organic transistor including an organic semiconductor having high crystallinity without loosing an interface between an organic semiconductor of a channel where carriers are spread out and a gate insulating layer and deteriorating a yield. A semiconductor device according to the present invention has a stacked structure of organic semiconductor layers, and at least the upper organic semiconductor layer is in a polycrystalline or a single crystalline state and the lower organic semiconductor layer is made of a material serving as a channel. Carrier mobility can be increased owing to the upper organic semiconductor layer having high crystallinity; thus, insufficient contact due to the upper organic semiconductor layer can be compensated by the lower organic semiconductor layer.

Abstract: A light-emitting diode package 1 of the present invention is a light-emitting diode package including: a diode group 2D made of a plurality of light-emitting diode chips 2 connected in series and a lead group 3 connected to the diode group 2D, in which the lead group 3 includes: a pair of external leads 31 and 32 as terminals of the diode group 2D and auxiliary leads 33 the number of which is one less than that of the light-emitting diode chips 2, in which the plurality of the light-emitting diode chips 2 are arranged in one line on a first external lead 31 of the pair of external leads 31 and 32, in which the auxiliary leads 33 are arranged on one or both sides of a row made of the plurality of light-emitting diode chips 2, and in which the adjacent light-emitting diode chips 2 of the plurality of light-emitting diode chips 2 are connected in series via the auxiliary leads 33.

Abstract: A semiconductor substrate, of GaAs with a semiconductor layer sequence applied on top of the substrate. The semiconductor layer sequence comprises a plurality of semiconductor layers of Al1-yGayAs1-xPx with 0?x?1 and 0?y?1. A number of the semiconductor layers respectively comprising a phosphorus component x which is greater than in a neighboring semiconductor layer lying thereunder in the direction of growth of the semiconductor layer sequence. Two semiconductor layers directly preceding the uppermost semiconductor layer of the semiconductor layer sequence have a smaller lattice constant than the uppermost layer.

Abstract: A semiconductor photodetector device (PD1) comprises a multilayer structure (LS1) and a glass substrate (1) optically transparent to incident light. The multilayer structure includes an etching stop layer (2), an n-type high-concentration carrier layer (3), an n-type light-absorbing layer (5), and an n-type cap layer (7) which are laminated. A photodetecting region (9) is formed near a first main face (101) of the multilayer structure, whereas a first electrode (21) is provided on the first main face. A second electrode (27) and a third electrode (31) are provided on a second main face (102). A film (10) covering the photodetecting region and first electrode is formed on the first main face. A glass substrate (1) is secured to the front face (10a) of this film.

Abstract: A metal ion transistor and related methods are disclosed. In one embodiment, the metal ion transistor includes a cell positioned in at least one isolation layer, the cell including a metal ion doped low dielectric constant (low-k) dielectric material sealed from each adjacent isolation layer; a first electrode contacting the cell on a first side; a second electrode contacting the cell on a second side; and a third electrode contacting the cell on a third side, wherein each electrode is isolated from each other electrode.

Abstract: Disclosed is a light emitting diode (LED) package having multiple molding resins. The LED package includes a pair of lead terminals. At least portions of the pair of lead terminals are embedded in a package main body. The package main body has an opening through which the pair of lead terminals is exposed. An LED die is mounted in the opening and electrically connected to the pair of lead terminals. A first molding resin covers the LED die. A second molding resin with higher hardness than the first molding resin covers the first molding resin. Therefore, stress to be imposed on the LED die can be reduced and the deformation of the molding resins can be prevented.

Abstract: A light emitting device includes: a light emitting layer; an n-type contact layer made of a compound provided on the light emitting layer; a composition modulation layer provided on the n-type contact layer; and a transparent electrode provided on the composition modulation layer. The composition modulation layer consists of a plurality of elements which constitute the compound. A composition ratio of one of the plurality of elements is higher in the composition modulation layer than in the compound. Alternatively, the light emitting device includes: a light emitting layer; an n-type contact layer made of a compound provided on the light emitting layer; a metal layer provided on the n-type contact layer; and a transparent electrode provided on the metal layer. The metal layer is made of a metal having a lower work function than the compound.