Patents Examined by Diana C Garrity
  • Patent number: 7524708
    Abstract: A light emitting diode includes a substrate tilted toward first and second directions simultaneously, a first cladding layer formed with a semiconductor material of a first conductive type on the substrate, an active layer formed on the first cladding layer, and a second cladding layer formed with a semiconductor material of a second conductive type on the active layer, wherein concavo-convexes are formed on the interfaces of the first cladding layer, the second cladding layer, and the active layer.
    Type: Grant
    Filed: February 22, 2006
    Date of Patent: April 28, 2009
    Assignee: NeosemiTech Corporation
    Inventors: Joon-Suk Song, Soo-Hyung Seo, Myung-Hwan Oh
  • Patent number: 7521803
    Abstract: A semiconductor device, has a semiconductor substrate; a first insulating film which is disposed above the semiconductor substrate; a second insulating film which is disposed above the first insulating film; a wiring which is disposed in the first insulating film and has a plug connecting part; a plug which is disposed in the second insulating film and connected to the plug connecting part; a plurality of first dummy wirings which are disposed in a first area near the plug connecting part in the first insulating film; and a plurality of second dummy wirings which are disposed in a second area near the wiring excepting the plug connecting part in the first insulating film, and have at least either a width smaller than that of the first dummy wirings or a pattern coverage ratio larger than that of the first dummy wirings.
    Type: Grant
    Filed: October 20, 2006
    Date of Patent: April 21, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshiyuki Morita, Takeshi Nishioka
  • Patent number: 7485922
    Abstract: In a semiconductor device of the present invention, an N type epitaxial layer is formed on a P type single crystal silicon substrate. The substrate and the epitaxial layer are partitioned into a plurality of element formation regions by isolation regions. Each of the isolation regions is formed of a P type buried diffusion layer and a P type diffusion layer coupled thereto. The P type buried diffusion layer is joined to N type buried diffusion layers on both sides thereof to form PN junction regions. On the other hand, the P type diffusion layer is joined to N type diffusion layers on both sides thereof to form PN junction regions. This structure suppresses extension of widthwise diffusion of the P type buried diffusion layer and the P type diffusion layer, thus making it possible to reduce the device size.
    Type: Grant
    Filed: September 26, 2006
    Date of Patent: February 3, 2009
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Seiji Otake, Ryo Kanda, Shuichi Kikuchi
  • Patent number: 7443016
    Abstract: A semiconductor device and a fabrication method thereof are provided. An opening having at least one slanted side is formed on a substrate. At least one chip and at least one passive component are mounted on the substrate. An encapsulant having a cutaway corner is formed on the substrate to encapsulate the chip and the passive component, wherein the cutaway corner of the encapsulant is spaced apart from the slanted side of the opening by a predetermined distance. A singulation process is performed to cut the encapsulant to form a package with a chamfer. The package is embedded in a lid to form the semiconductor device, wherein a portion of the substrate located between the slanted side of the opening and the cutaway corner of the encapsulant is exposed from the encapsulant to form an exposed portion. The present invention also provides a carrier for the semiconductor device.
    Type: Grant
    Filed: October 13, 2005
    Date of Patent: October 28, 2008
    Assignee: Silicon Precision Industries Co., Ltd.
    Inventors: Yun-Lung Tsai, Yu-Chieh Tsai, Chien-Chih Chen, Chien-Ping Huang