Abstract: The present disclosure provides an electronic device. The electronic device includes a first resin layer, having a first resin layer main surface and a first resin layer inner surface; a first conductor, having a first conductor main surface and a first conductor inner surface; a first wiring layer, formed adjacent to the first resin layer main surface and connected to the first conductor main surface; a first electronic component, electrically connected with the first wiring layer; a second resin layer, having a second resin layer main surface facing same direction as the first resin layer main surface and a second resin layer inner surface being in contact with the first resin layer main surface; an external electrode; and a second conductor, penetrating the second resin layer, wherein the second conductor is disposed on a periphery of the first electronic component.

Abstract: The present disclosure provides a chip structure and a semiconductor structure. The chip structure includes: a substrate; a functional region located on the substrate; a guard ring structure surrounding the functional region; and an auxiliary bonding region located above the guard ring structure, where there is an overlapping region between a projection of at least part of the auxiliary bonding region on the substrate and a projection of the guard ring structure on the substrate.

Abstract: An electronic device can include a first die, a second die, and an interconnect. The first die or the second die has a principal function as a power module or a memory. The first die includes a first bond pad, and the second die includes a second bond pad. The device sides of the first and second dies are along the same sides as the first and second bond pads. In an embodiment, the first die and the second die are in a chip first, die face-up configuration. The first and the second bond pads are electrically connected along a first solderless connection that includes the interconnect. In another embodiment, each material within the electrical connection between the first and the second bond pads has a flow point or melting point temperature of at least 300° C.

Abstract: An electromagnetic interference (EMI) shielding package structure, a manufacturing method thereof, and an electronic assembly are provided. The EMI shielding package structure includes a carrier, at least one chip mounted on a first board surface of the carrier, an encapsulant formed on the carrier and packaging the at least one chip, an EMI shielding layer formed on an outer surface of the encapsulant, and an insulating layer. The insulating layer includes a spraying portion and a capillary permeating portion. The spraying portion is formed at least part of an outer surface of the EMI shielding layer. The capillary permeating portion is formed by extending from a bottom end of the spraying portion toward a second board surface of the carrier through capillarity, and the capillary permeating portion covers a bottom edge of the EMI shielding layer.

Abstract: A semiconductor device has a substrate. A first electrical component and second electrical component are disposed over the substrate. A conductive pillar is formed over the substrate between the first electrical component and second electrical component. A first shielding layer is formed over the first electrical component and conductive pillar by jet printing conductive material. A second shielding layer is formed over the first electrical component and second electrical component by sputtering, spraying, or plating conductive material. An insulating layer is optionally formed between the first shielding layer and second shielding layer by jet printing insulating material over the first shielding layer.

Abstract: A semiconductor device assembly is provided. The assembly includes a substrate having an upper surface on which is disposed a first device contact, a keep-out region extending from a first side surface of the substrate to a second side surface of the substrate opposite the first, and at least one trace coupled to the first device contact and extending across the keep out region towards a third side surface of the substrate. The assembly further includes at least one semiconductor device disposed over the upper surface of the substrate and coupled to the first device contact. The keep-out region of the substrate is free from conductive structures other than the at least one trace.

Abstract: A memory device includes: a substrate having a memory region and an external region; a first conductor, in the memory region, being arranged apart from the substrate in a first direction; second and third conductors, in the external region, being arranged apart from the first conductor in a second direction; a first member between the first and second conductors; a second member between the second and third conductors; and an insulating member between the first and second members. The first and second members each includes a lower portion extending in the first direction and reaching below the second conductor and an upper portion having a side surface outside an extension of a side surface of the lower portion. The insulating member includes lower and upper ends located below and above each of the upper portions, respectively.

Abstract: A display device includes a display area which displays a screen, an inner line disposed outside the display area, and extending to surround the display area, an outer line disposed outside the inner line, a contact pattern overlapping with the inner line and the outer line and electrically connecting the inner line and the outer line to each other, and a connection line disposed between the inner line and the outer line to electrically connect the inner line and the outer line to each other, a contact area where the contact pattern overlaps with the outer line and physically contact the outer line, and a non-contact area where the contact pattern overlaps with the outer line and does not physically contact the outer line. The connection line is disposed within the non-contact area.

Abstract: A method for forming a three-dimensional (3D) memory device includes forming a dielectric stack including a plurality of first/second dielectric layer pairs over a substrate, forming a plurality of channel structures extending in a lateral direction in a core region of the dielectric stack, forming a staircase structure including a plurality of stairs extending along the lateral direction in a staircase region of the dielectric stack, forming a first drain-select-gate (DSG) cut opening extending in the lateral direction in the core region and a second DSG cut opening in the staircase region, and forming a first DSG cut structure in the first DSG cut opening and a second DSG cut structure in the second DSG cut opening.

Abstract: A semiconductor device of the disclosure includes a peripheral circuit structure including a peripheral transistor, a semiconductor layer on the peripheral circuit structure, a source structure on the semiconductor layer, a gate stack structure disposed on the source structure and including insulating patterns and conductive patterns alternately stacked, a memory channel structure electrically connected to the source structure and penetrating the gate stack structure, a support structure penetrating the gate stack structure and the source structure, and an insulating layer covering the gate stack structure, the memory channel structure and the support structure. The support structure includes an outer support layer contacting side walls of the insulating patterns and side walls of the conductive patterns, and a support pattern and an inner support layer contacting an inner side wall of the outer support layer.

Abstract: A thin-film transistor includes: a base substrate; a semiconductor layer on the base substrate, the semiconductor layer including a first oxide semiconductor layer and a second oxide semiconductor layer on the first oxide semiconductor layer, the second oxide semiconductor layer having a Hall mobility smaller than a Hall mobility of the first oxide semiconductor layer; a gate electrode spaced apart from the semiconductor layer and partially overlapping the semiconductor layer; a gate insulating layer between the semiconductor layer and the gate electrode; and a first mixture area between the first oxide semiconductor layer and the second oxide semiconductor layer. The second oxide semiconductor layer includes gallium (Ga) of 40 atom % or more in comparison with a total metallic element with respect to a number of atoms. The first mixture area, the first oxide semiconductor layer, and the second oxide semiconductor layer are formed by metal-organic chemical vapor deposition (MOCVD).

Abstract: A semiconductor package including a semiconductor chip, an interposer on the semiconductor chip, and a molding layer covering at least a portion of the semiconductor chip and at least a portion of the interposer may be provided. The interposer includes a interposer substrate and a heat dissipation pattern penetrating the interposer substrate and electrically insulated from the semiconductor chip. The heat dissipation pattern includes a through electrode disposed in the interposer substrate and an upper pad disposed on an upper surface of the interposer substrate and connected to the through electrode. The molding layer covers at least a portion of a sidewall of the upper pad and the upper surface of the interposer substrate. At least a portion of an upper surface of the upper pad is not covered by the molding layer.

Abstract: A cooling structure having a first side and a second side opposite the first side can be formed through a method comprising, forming an inlet and an outlet in a first substrate, forming at least one channel on the second side of the first substrate, wherein the at least one channel is in fluid communication with the inlet and outlet, forming a plurality of nozzles on the first side of a second substrate, and forming a plurality of channels on the second side of the second substrate opposite the first side of the second substrate. The plurality of channels is aligned with the plurality of nozzles, and the second side of the first substrate is bonded to the first side of the second substrate.

Abstract: Provided is a resistive memory structure and a manufacturing method thereof. The resistive memory structure includes a substrate, a dielectric layer, a resistive memory device, a hard mask layer, and a spacer. The dielectric layer is located on the substrate. The dielectric layer has an opening. The resistive memory device is located in the opening and has a protrusion outside the opening. The resistive memory device includes a first electrode, a variable resistance layer, and a second electrode. The variable resistance layer is located on the first electrode. The second electrode is located on the variable resistance layer. The hard mask layer covers a top surface of the variable resistance layer. The spacer covers a sidewall of the variable resistance layer in the protrusion.

Abstract: A method used in forming integrated circuitry comprises forming a stack comprising vertically-alternating first tiers and second tiers. The stack comprises a cavity therein that comprises a stair-step structure. Sidewalls of the cavity and steps of the stair-step structure are lined with an insulator material. Insulative material is formed in the cavity radially inward of the insulator material. An upper portion of the insulative material is removed from the cavity to leave the insulative material in a bottom of the cavity over the stair-step structure. After the removing, insulating material is formed in the cavity above the insulative material. Other embodiments, including structure independent of method, are disclosed.

Abstract: An organic light emitting display device including a light extraction reduction preventing layer disposed between a display unit disposed on a substrate and an encapsulation layer for protecting the display unit, which improves light emission efficiency by reducing an amount of light dissipating while light generated from an emission layer of the display unit is extracted to the outside.

Abstract: Systems, methods, and devices for a ball grid array with non-linear conductive routing are described herein. Systems include a printed circuit board, a microprocessor, a ball grid array, and a substrate. The ball grid array includes a first solder ball and a second solder ball. The substrate includes a non-linear conductive routing electrically coupling the first solder ball and the second solder ball. The non-linear conductive routing includes a first routing section connected to the first solder ball, and a second routing section connected to the second solder ball. The non-linear conductive routing further includes a third routing section connected to the first routing section, and a fourth routing section connected to the third routing section, wherein each of the third routing section and the fourth routing section are rotational routing sections configured to flow current in a first rotational direction.

Abstract: An electronic device includes an object substrate, an electronic unit and an electrostatic discharge protective unit. The object substrate includes a bonding pad. The electronic unit includes an electrode bonding on the bonding pad. The electrostatic discharge protective unit is located in the object substrate and electrically connected to the bonding pad.

Abstract: A three-dimensional semiconductor memory device includes a substrate including a cell array region and a connection region and an electrode structure including first and second electrodes alternatingly and vertically stacked on the substrate and having a stair-step structure on the connection region. Each of the first and second electrodes may include electrode portions provided on the cell array region to extend in a first direction and to be spaced apart from each other in a second direction perpendicular to the first direction, an electrode connecting portion provided on the connection region to extend in the second direction and to horizontally connect the electrode portions to each other, and protrusions provided on the connection region to extend from the electrode connecting portion in the first direction and to be spaced apart from each other in the second direction.

Abstract: A microelectronic device comprises a stack structure, a stadium structure within the stack structure, a source tier underlying the stack structure, and a masking structure. The stack structure has tiers each comprising a conductive structure and an insulating structure. The stadium structure comprises a forward staircase structure, a reverse staircase structure, and a central region horizontally interposed between the forward staircase structure and the reverse staircase structure. The source tier comprises discrete conductive structures within horizontal boundaries of the central region of the stadium structure and horizontally separated from one another by dielectric material. The masking structure is confined within the horizontal boundaries of the central region of the stadium structure and is vertically interposed between the source tier and the stack structure.