Abstract: A semiconductor package, a semiconductor device and a shielding housing for a semiconductor package are provided. The semiconductor package includes a semiconductor chip having a first region and a second region beside the first region; and a shielding housing encasing the semiconductor chip, made of a magnetic permeable material, and including a first shielding plate, a second shielding plate opposite to the first shielding plate and a shielding wall extending between the first shielding plate and the second shielding plate. The first shielding plate has an opening exposing the first region and includes a raised portion surrounding the opening and a flat portion beside the raised portion and shielding the second region. A first distance from a level of the semiconductor chip to an outer surface of the raised portion is greater than a second distance from the level to an outer surface of the flat portion.

Abstract: Aspects of the disclosure provide a method of forming a semiconductor apparatus including a first portion and a second portion. The first portion is formed on a first substrate and includes at least one first semiconductor device. The second portion is formed on a second substrate including a bulk substrate material and includes at least one second semiconductor device. A carrier substrate is attached to the second portion. The bulk substrate material is removed from the second substrate. The first portion and the second portion are bonded to form the semiconductor apparatus where the at least one second semiconductor device is stacked above the at least one first semiconductor device along a Z direction substantially perpendicular to a substrate plane of the first substrate. The at least one first semiconductor device and the at least one second semiconductor device are positioned between the carrier substrate and the first substrate.

Abstract: A semiconductor device has a first package layer. A first shielding layer is formed over the first package layer. The first shielding layer is patterned to form a redistribution layer. An electrical component is disposed over the redistribution layer. An encapsulant is deposited over the electrical component. A second shielding layer is formed over the encapsulant. The second shielding layer is patterned. The patterning of the first shielding layer and second shielding layer can be done with a laser. The second shielding layer can be patterned to form an antenna.

Abstract: Disclosed is a method for manufacturing a semiconductor device which includes: a semiconductor chip; a substrate and/or another semiconductor chip; and an adhesive layer interposed therebetween. This method comprises the steps of: heating and pressuring a laminate having: the semiconductor chip; the substrate; the another semiconductor chip or a semiconductor wafer; and the adhesive layer by interposing the laminate with pressing members for temporary press-bonding to thereby temporarily press-bond the substrate and the another semiconductor chip or the semiconductor wafer to the semiconductor chip; and heating and pressuring the laminate by interposing the laminate with pressing members for main press-bonding, which are separately prepared from the pressing members for temporary press-bonding, to thereby electrically connect a connection portion of the semiconductor chip and a connection portion of the substrate or the another semiconductor chip.

Abstract: Provided are an organic light-emitting display panel and a display device. The organic light-emitting display includes an array substrate and organic light-emitting components each having an anode, a cathode and an organic functional layer. The organic functional layer includes an organic light-emitting layer, a first electron transmission layer, and a hole injection layer. LUMO1 and LUMO4 satisfy: |LUMO1?LUMO4|<1.7 eV. HOMO5 and HOMO4 satisfy: |HOMO5?HOMO4|<1 eV. A work function ?1 of the first dopant and a work function ?4 of the cathode satisfy: ?1<?4, and a work function ?2 of the second dopant and a work function ?3 of the anode satisfy: ?2>?3.

Abstract: Embodiments of semiconductor devices and fabrication methods thereof are disclosed. In an example, a semiconductor device includes a first semiconductor structure, a second semiconductor structure, and an interposer structure vertically between the first and second semiconductor structures. The first semiconductor structure includes a plurality of logic process-compatible devices and a first bonding layer comprising a plurality of first bonding contacts. The second semiconductor structure includes an array of NAND memory cells and a second bonding layer comprising a plurality of second bonding contacts. The interposer structure includes a first interposer bonding layer having a plurality of first interposer contacts disposed at a first side of the interposer structure, and a second interposer bonding layer having a plurality of second interposer contacts disposed at a second side opposite of the first side of the interposer structure.

Abstract: A flip-chip process is to provide a pressing jig with a channel, so that the pressing jig grips a chip module by vacuum suction through the channel, and the chip module can be bonded onto a circuit board via a plurality of solder bumps through the pressing jig, and then a heating device is provided to heat the plurality of solder bumps and reflow the plurality of solder bumps. Therefore, the chip module can be vacuum-gripped by the pressing jig to suppress deformation of the chip module, so that the solder bumps can effectively connect to corresponding contacts of the circuit board.

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses.

Abstract: A semiconductor component includes at least two functional units which are identical to one another and are wired to one another, the identical functional units each include at least one gate finger, at least one source finger and at least one drain finger; the wiring comprising conductor tracks. A first track connects the gate fingers respectively, a second track connects the source fingers respectively, and a third track connects the drain fingers of the at least two same functional units, respectively.

Abstract: A package structure and a formation method of a package structure are provided. The method includes placing a semiconductor die over a redistribution structure and placing a conductive feature over the redistribution structure. The conductive feature has a support element and a solder element. The solder element extends along surfaces of the support element. The method also includes stacking an interposer substrate over the redistribution structure. The interposer substrate extends across the semiconductor die. The method further includes forming a protective layer to surround the conductive feature and the semiconductor die.

Abstract: A vertical memory device is provided including a first structure on a substrate. The first structure includes gate patterns spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate to form a plurality of layers. A second structure is connected to the first structure. The second structure includes pad patterns electrically connected to the gate patterns of a respective one of the layers. A channel structure passes through the gate patterns. A first contact plug passes through the second structure and electrically connects with a pad pattern of one of the layers. The first contact plug is electrically insulated from gate patterns of other layers. At least one bent portion is included at each of a sidewall of the channel structure and a sidewall of the first contact plug.

Abstract: An electronic device package includes: a substrate including a central region, and a first side region and a second side region at opposite sides of the central region; a first component in the first side region or the second side region, the first component having a first height above a surface of the substrate; a second component in the central region, the second component having a second height above the surface of the substrate that is lower than the first height; a reinforcement member in the central region and overlapping the second component, the reinforcement member having a third height above the surface of the substrate that is lower than the first height and higher than the second height; and an encapsulation member covering the first component and the second component.

Abstract: A three-dimensional memory device includes a source contact layer overlying a substrate, an alternating stack of insulating layers and electrically conductive layers located overlying the source contact layer, and a memory opening fill structure located within a memory opening extending through the alternating stack and the source contact layer. The memory opening fill structure includes a composite semiconductor channel and a memory film laterally surrounding the composite semiconductor channel. The composite semiconductor channel includes a pedestal channel portion having controlled distribution of n-type dopants that diffuse from the source contact layer with a lower diffusion rate provided by carbon doping and smaller grain sizes, or has arsenic doping providing limited diffusion into the vertical semiconductor channel.

Abstract: A semiconductor device includes an inductance structure and a shielding structure. The shielding structure is arranged to at least partially shield the inductance structure from external electromagnetic fields. The shielding structure includes a shielding structure portion arranged along a side of the inductance structure such that the shielding structure portion is around at least a portion of a perimeter of the inductance structure.

Abstract: A display module including a glass substrate; a thin film transistor layer disposed in a first area of the glass substrate; a plurality of connection pads disposed in a second area extending from the first area of the glass substrate and electrically connected to the thin film transistor layer; a plurality of test pads disposed in a third area extending from the second area of the glass substrate and electrically connected to the plurality of connection pads, respectively, and a plurality of connection wirings electrically connecting the plurality of connection pads and the plurality of test pads.

Abstract: An electronic package is formed by disposing an electronic element and a lead frame having a plurality of conductive posts on a carrier structure having an antenna function, and encapsulating the electronic element and the lead frame with an encapsulant. The encapsulant is defined with a first encapsulating portion and a second encapsulating portion lower than the first encapsulating portion. The electronic element is positioned in the first encapsulating portion, and the plurality of conductive posts are positioned in the second encapsulating portion. End surfaces of the plurality of conductive posts are exposed from a surface of the second encapsulating portion so as to be electrically connected to a connector.

Abstract: A semiconductor device includes; gate layers stacked on a substrate, a channel layer extending through the gate layers, a string select gate layer disposed on the channel layer and a string select channel layer extending through the string select gate layer to contact the channel layer. The string select channel layer includes a first portion below the string select gate layer including a first protruding region, a second portion extending through the string select gate layer, and a third portion above the string select gate layer including a second protruding region.

Abstract: An electronic device includes a first electrode and a second electrode facing each other, an emission layer comprising a plurality of quantum dots, wherein the emission layer is disposed between the first electrode and the second electrode; a first charge auxiliary layer disposed between the first electrode and the emission layer; and an optical functional layer disposed on the second electrode on a side opposite the emission layer, wherein the first electrode includes a reflecting electrode, wherein the second electrode is a light-transmitting electrode, wherein a region between the optical functional layer and the first electrode comprises a microcavity structure, and a refractive index of the optical functional layer is greater than or equal to a refractive index of the second electrode.

Abstract: A nonvolatile memory device with improved product reliability and a method of fabricating the same is provided. The nonvolatile memory device comprises a substrate, a first mold structure disposed on the substrate and including a plurality of first gate electrodes, a second mold structure disposed on the first mold structure and including a plurality of second gate electrodes and a plurality of channel structures intersecting the first gate electrodes and the second gate electrodes by penetrating the first and second mold structures, wherein the first mold structure includes first and second stacks, which are spaced apart from each other, and the second mold structure includes a third stack, which is stacked on the first stack, a fourth stack, which is stacked on the second stack, and first connecting parts, which connect the third and fourth stacks.

Abstract: A wire bonding method includes bonding a tip of a wire provided through a clamp and a capillary onto a bonding pad of a chip, moving the capillary to a connection pad of a substrate corresponding to the bonding pad, bonding the wire to the connection pad to form a bonding wire connecting the bonding pad to the connection pad, before the capillary is raised from the connection pad, applying a electrical signal to the wire to detect whether the wire and the connection pad are in contact with each other, changing a state of the clamp to a closed state when the wire is not in contact with the connection pad and maintaining the state of the clamp in an open state when the wire is in contact with the connection pad, and raising the capillary from the connection pad while maintaining the state of the clamp.