Patents Examined by Didarul A Mazumder
  • Patent number: 11127711
    Abstract: According to one embodiment, a semiconductor device includes a first wafer, a first wiring layer, a first insulating layer, a first electrode, a second wafer, a second wiring layer, a second insulating layer, a second electrode, and a first layer. The first electrode includes a first surface, a second surface, a third surface, and a fourth surface. The second electrode includes a fifth surface, a sixth surface, a seventh surface, a second side surface, and an eighth surface. The first layer is provided between the fourth surface and a portion of the first insulating layer that surrounds the fourth surface, and is provided away from the third surface in the first direction.
    Type: Grant
    Filed: March 3, 2020
    Date of Patent: September 21, 2021
    Assignee: KIOXIA CORPORATION
    Inventor: Masato Shini
  • Patent number: 11127722
    Abstract: A stack package includes sub-packages vertically stacked. Each of the sub-packages includes a semiconductor chip having a power pad and a signal pad, a first interposer bridge having a signal through via and a second power through via, and a second interposer bridge having a first power through via. Each of the sub-packages further includes a signal redistributed layer pattern extending to electrically connect the signal pad to a signal connection part and a power redistributed layer pattern to electrically connect the power pad to the first and second power through vias. An upper sub-package of the sub-packages is rotated relative to a lower sub-package, and the rotated upper sub-package is stacked on a lower sub-package of the sub-packages.
    Type: Grant
    Filed: June 4, 2020
    Date of Patent: September 21, 2021
    Assignee: SK hynix Inc.
    Inventor: Bok Kyu Choi
  • Patent number: 11127650
    Abstract: The present disclosure provides a semiconductor device package. The semiconductor device package includes a first die, a second die, and a thermal dissipation element. The first die has a first surface. The second die is disposed on the first surface. The thermal dissipation element is disposed on the first surface. The thermal dissipation element includes a first portion extending in a first direction substantially parallel to the first surface and partially covered by the second die and a second portion extending in a second direction substantially perpendicular to the first surface to be adjacent to an edge of the second die.
    Type: Grant
    Filed: February 24, 2020
    Date of Patent: September 21, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chien Lin Chang Chien, Chiu-Wen Lee, Hung-Jung Tu, Chang Chi Lee, Chin-Li Kao
  • Patent number: 11127656
    Abstract: A semiconductor device comprises a semiconductor body and an electrically conductive via which extends through at least a part of the semiconductor body, where the via has a lateral size which is given in a first lateral direction that is perpendicular to a vertical direction given by the main axis of extension of the via and where the via has a top side and a bottom side that faces away from the top side. The semiconductor device further comprises an electrically conductive etch-stop layer arranged at the bottom side of the via in a plane which is parallel to the first lateral direction, and at least one electrically conductive contact layer at the bottom side of the via in a plane which is parallel to the first lateral direction. The lateral extent in the first lateral direction of the etch-stop layer is larger than the lateral size of the via and the lateral extent in the first lateral direction of the contact layer is smaller than the lateral size of the via.
    Type: Grant
    Filed: February 14, 2018
    Date of Patent: September 21, 2021
    Assignee: AMS AG
    Inventors: Jochen Kraft, Georg Parteder, Anderson Singulani, Raffaele Coppeta, Franz Schrank
  • Patent number: 11121103
    Abstract: A semiconductor package is provided which includes a package substrate, a first die, a second die, an interconnection member and a plurality of bonding wires. The first die is disposed on the package substrate. The second die is disposed over the first die. The interconnection member includes a connection plate, a plurality of redistribution structures and a plurality of bumps. The connection plate is connected to the first die. The redistribution structures are connected to the second die. The bumps couple the connection plate to the redistribution structures. The bonding wires couple the interconnection member to the package substrate and the first die.
    Type: Grant
    Filed: March 4, 2020
    Date of Patent: September 14, 2021
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Wu-Der Yang
  • Patent number: 11121096
    Abstract: Systems and/or techniques associated with active control of electronic package warpage are provided. In one example, a system includes an electronic package and an integrated circuit. The electronic package includes a patterned structural material associated with a mechanical characteristic that changes in response to an applied condition. The integrated circuit controls the applied condition associated with the patterned structural material based on sensor data associated with a status of the electronic package.
    Type: Grant
    Filed: March 21, 2019
    Date of Patent: September 14, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Katsuyuki Sakuma, Shidong Li
  • Patent number: 11121260
    Abstract: A thin-film transistor, a display device including a thin-film transistor, and a method of manufacturing a thin-film transistor are provided. A thin-film transistor includes: a base substrate, a semiconductor layer on the base substrate, the semiconductor layer including: a first oxide semiconductor layer, and a second oxide semiconductor layer on the first oxide semiconductor layer, the second oxide semiconductor layer having a Hall mobility smaller than a Hall mobility of the first oxide semiconductor layer, and a gate electrode spaced apart from the semiconductor layer and partially overlapping the semiconductor layer, wherein a concentration of gallium (Ga) in the second oxide semiconductor layer is higher than a concentration of gallium (Ga) in the first oxide semiconductor layer.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: September 14, 2021
    Assignee: LG Display Co., Ltd.
    Inventors: SeHee Park, JungSeok Seo, PilSang Yun, Jeyong Jeon, Jaeyoon Park, ChanYong Jeong
  • Patent number: 11114485
    Abstract: A device may include a multispectral filter array disposed on the substrate. The multi spectral filter array may include a first metal mirror disposed on the substrate. The multi spectral filter may include a spacer disposed on the first metal mirror. The spacer may include a set of layers. The spacer may include a second metal mirror disposed on the spacer. The second metal mirror may be aligned with two or more sensor elements of a set of sensor elements.
    Type: Grant
    Filed: April 29, 2020
    Date of Patent: September 7, 2021
    Assignee: VIAVI Solutions Inc.
    Inventor: Georg J. Ockenfuss
  • Patent number: 11114508
    Abstract: A display panel and a display device are described. The display panel includes three-pixel units representing three different colors. In each pixel unit there are six sub-pixels dividing an anode formed on the pixel unit; in the same pixel unit, anodes of all sub-pixels are insulated from each other; three closest sub-pixels of different colors form a main pixel; and a center point of the main pixel is in one-to-one association with an image point of a display source image, and the image point falls within 10% proximity of the associated center point of the main pixel. The six sub-pixels in each pixel unit are formed simultaneously in a manner of pixel printing.
    Type: Grant
    Filed: November 5, 2019
    Date of Patent: September 7, 2021
    Assignee: SHANGHAI TIANMA MICRO-ELECTRONICS CO., LTD.
    Inventors: Jialing Li, Sitao Huo
  • Patent number: 11114026
    Abstract: A display apparatus includes a plurality of pixels, each of the pixels including an organic light emitting diode, a first transistor providing a driving current to operate the organic light emitting diode, a second transistor including a gate electrode that receives a first scan signal, a first electrode that receives a data signal, and a second electrode electrically connected to the first electrode of the first transistor, a storage capacitor including a first electrode receiving a first power voltage and a second electrode electrically connected to the gate electrode of the first transistor, and a color accuracy enhancement transistor that applies a first back bias voltage to the first transistor in response to a color accuracy enhancement signal.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: September 7, 2021
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Gun Hee Kim, Do Hyung Kim, Hyeonsik Kim, Sangho Park, Joo-Sun Yoon, Joohee Jeon
  • Patent number: 11107800
    Abstract: A display device can include a substrate on which a semiconductor element and a common electrode are disposed; a light emitting diode which is disposed on the substrate and includes an n-type layer, a light emitting layer, and a p-type layer; an insulating layer disposed on the substrate and the light emitting diode; and a first connecting electrode which is connected to the light emitting diode and the semiconductor element. Accordingly, it is possible to minimize defects which can be caused during a process of disposing the light emitting diode on the substrate.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: August 31, 2021
    Assignee: LG DISPLAY CO., LTD.
    Inventors: HyeonHo Son, HanSaem Kang, Bogyun Chung, Sungeun Bae, HyungJu Park, Eunjeong Shin, Jeenmoon Yang
  • Patent number: 11101268
    Abstract: Techniques are disclosed for forming transistors employing non-selective deposition of source and drain (S/D) material. Non-selectively depositing S/D material provides a multitude of benefits over only selectively depositing the S/D material, such as being able to attain relatively higher dopant activation, steeper dopant profiles, and better channel strain, for example.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: August 24, 2021
    Assignee: Intel Corporation
    Inventors: Karthik Jambunathan, Scott J. Maddox, Ritesh Jhaveri, Pratik A. Patel, Szuya S. Liao, Anand S. Murthy, Tahir Ghani
  • Patent number: 11101411
    Abstract: Solid-state light emitting devices including light-emitting diodes (LEDs), and more particularly packaged LEDs are disclosed. LED packages are disclosed that include an LED chip with multiple discrete active layer portions mounted on a submount. The LED packages may further include wavelength conversion elements and light-altering materials. The multiple discrete active layer portions may be electrically connected in series, parallel, or in individually addressable arrangements. The LED chip with the multiple discrete active layer portions may provide the LED package with improved brightness, improved alignment, simplified manufacturing, and reduced costs.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: August 24, 2021
    Assignee: CreeLED, Inc.
    Inventors: Peter Scott Andrews, Colin Blakely, Jesse Reiherzer, Arthur F. Pun
  • Patent number: 11094615
    Abstract: A semiconductor device, a drain electrode terminal supporting the semiconductor device and connected directly to a drain electrode pad, a source electrode terminal connected to a source electrode pad, and a gate electrode terminal are provided, wherein the source electrode terminal includes a wire post, a first lead extending from one end of the wire post, and a second lead extending from another end of the wire post, wherein the source electrode pad and the wire post of the source electrode terminal are connected to each other through a plurality of bonding wires, and wherein the semiconductor device, a surface, supporting the semiconductor device thereon, of the drain electrode terminal, the wire post of the source electrode terminal, the bonding wires, and part of the gate electrode terminal are covered with a mold resin.
    Type: Grant
    Filed: September 13, 2018
    Date of Patent: August 17, 2021
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventor: Hisato Michikoshi
  • Patent number: 11094689
    Abstract: An electronic component includes a first contact point for n-side contacting, a second contact point for p-side contacting, and a protective diode, which is connected antiparallel to the first contact point and to the second contact point. The protective diode includes a first diode structure which is p-conductive and a second diode structure which is n-conductive. The first diode structure is formed as a layer which overlaps in places with the first contact point in a first overlap region. The second diode structure is formed as a layer which overlaps in places with the second contact point in a second overlap region. The first diode structure and the second diode structure overlap each other in a third overlap region.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: August 17, 2021
    Assignee: OSRAM OLED GmbH
    Inventors: Ivar Tangring, Thomas Schlereth
  • Patent number: 11094619
    Abstract: A package and method of making a package. In one example, the package includes an at least partially electrically conductive carrier, a passive component mounted on the carrier, and an at least partially electrically conductive connection structure electrically connecting the carrier with the component and comprising spacer particles configured for spacing the carrier with regard to the component.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: August 17, 2021
    Assignee: Infineon Technologies AG
    Inventors: Manfred Schindler, Franz-Peter Kalz, Volker Strutz
  • Patent number: 11088052
    Abstract: A surface mount electronic device providing an electrical connection between an integrated circuit (IC) and a printed circuit board (PCB) is provided and includes a die and a dielectric material formed to cover portions of the die. Pillar contacts are electrically coupled to electronic components in the die and the pillar contacts extend from the die beyond an outer surface of the die. A conductive ink is printed on portions of a contact surface of the electronic device package and forms electrical terminations on portions of the dielectric material and electrical connector elements that connect an exposed end surface of the pillar contacts to the electrical terminations.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: August 10, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Abram M. Castro
  • Patent number: 11088235
    Abstract: A display panel and a display device are provided. The resistance of a first equivalent resistor is set to be larger than the resistance of a second equivalent resistor so that voltage across the first equivalent resistor can be higher. In this way, when a second type of sub-pixel is driven to be lightened, and a first type of sub-pixel is driven not to be lightened, the first type of sub-pixel can be avoided from being lightened, due to the higher voltage across the first equivalent resistor despite leakages current, thus alleviating a display abnormality, and improving a display effect.
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: August 10, 2021
    Assignee: SHANGHAI TIANMA AM-OLED CO., LTD.
    Inventors: Mengmeng Zhang, Xingyao Zhou, Yue Li, Shuai Yang
  • Patent number: 11088099
    Abstract: A first conductive material having a first hardness is disposed within a recess or opening of a microelectronic component, in a first preselected pattern, and forms a first portion of an interconnect structure. A second conductive material having a second hardness different from the first hardness is disposed within the recess or opening in a second preselected pattern and forms a second portion of the interconnect structure.
    Type: Grant
    Filed: December 2, 2019
    Date of Patent: August 10, 2021
    Assignee: Invensas Bonding Technologies, Inc.
    Inventors: Rajesh Katkar, Cyprian Emeka Uzoh
  • Patent number: 11088293
    Abstract: Methods and apparatus form a photon absorber layer of a photodiode with characteristics conducive to applications such as, but not limited to, image sensors and the like. The absorber layer uses a copper-indium-gallium-selenium (CIGS) material with a gallium mole fraction of approximately 35% to approximately 70% to control the absorbed wavelengths while reducing dark current. Deposition temperatures of the absorber layer are controlled to less than approximately 400 degrees Celsius to produce sub-micron grain sizes. The absorber layer is doped with antimony at a temperature of less than approximately 400 degrees Celsius to increase the absorption.
    Type: Grant
    Filed: June 17, 2019
    Date of Patent: August 10, 2021
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Philip Hsin-Hua Li, Seshadri Ramaswami