Abstract: Deep gate-all-around semiconductor devices having germanium or group 111-V active layers are described. For example, a non-planar semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a hetero-junction between an upper layer and a lower layer of differing composition. An active layer is disposed above the hetero-structure and has a composition different from the upper and lower layers of the hetero-structure. A gate electrode stack is disposed on and completely surrounds a channel region of the active layer, and is disposed in a trench in the upper layer and at least partially in the lower layer of the hetero-structure. Source and drain regions are disposed in the active layer and in the upper layer, but not in the lower layer, on either side of the gate electrode stack.

Abstract: A first conductive material having a first hardness is disposed within a recess or opening of a microelectronic component, in a first preselected pattern, and forms a first portion of an interconnect structure. A second conductive material having a second hardness different from the first hardness is disposed within the recess or opening in a second preselected pattern and forms a second portion of the interconnect structure.

Abstract: The present technology includes a memory device. The memory device includes a stack structure including word lines and a select line, a vertical hole vertically penetrating the stack structure, and a memory layer, a channel layer, and a plug, sequentially formed along an inner side surface of the vertical hole. The plug includes a material layer having a fixed negative charge.

Abstract: A semiconductor device assembly is provided. The assembly includes a substrate including an upper surface having a plurality of internal contact pads and at least one grounding pad and a lower surface having a plurality of external contact pads. The assembly further includes a semiconductor die coupled to the plurality of internal contact pads, a conductive underfill dam coupled to the at least one grounding pad, and underfill material disposed at least between the semiconductor die and the substrate. The underfill material includes a fillet between the semiconductor die and the underfill dam. The assembly further includes a conductive EMI shield disposed over the semiconductor die, the fillet, and the conductive underfill dam.

Abstract: In some embodiments, a radio-frequency device can be manufactured by a method that includes forming or providing a substrate, fabricating or providing a flip chip die having a front side and a back side, and including an integrated circuit implemented on the front side, and mounting the front side of the flip chip die on the substrate. The method can further include implementing a shielding component over the back side of the flip chip die to provide electromagnetic shielding between a first region within or on the flip chip die and a second region away from the flip chip die.

Abstract: A semiconductor device includes a lower channel pattern and an upper channel pattern stacked on a substrate in a first direction perpendicular to a top surface of the substrate, lower source/drain patterns on the substrate and at a first side and a second side of the lower channel pattern, upper source/drain patterns stacked on the lower source/drain patterns and at a third side and a fourth side of the upper channel pattern, a first barrier pattern between the lower source/drain patterns and the upper source/drain patterns, and a second barrier pattern between the first barrier pattern and the upper source/drain patterns. the first barrier pattern includes a first material and the second barrier pattern includes a second material, wherein the first material and the second material are different.

Abstract: A package structure and a manufacturing method for the same are provided. The package structure includes a circuit, a mold sealing layer, a conductive metal board, and a conductive layer. The circuit board includes a substrate and a first electronic element disposed on the substrate. The mold sealing layer is disposed on the substrate and covers the first electronic element. The mold sealing layer has a top surface, a bottom surface corresponding to the top surface, and a side surface connected between the top surface and the bottom surface. The conductive metal board is disposed on the top surface and adjacent to the first electronic element. The conductive layer is disposed on the side surface and electrically connected to the conductive metal board. The conductive metal board and the conductive layer are each an independent component.

Abstract: A multifaceted capillary that can be used in a wire-bonding machine to create a multi-segment wire-bond is disclosed. The multifaceted capillary is shaped to apply added pressure and thickness to an outer segment of the multi-segment wire-bond that is closest to the wire loop. The added pressure eliminates a gap under a heel portion of the multi-segment wire-bond and the added thickness increases a mechanical strength of the heel portion. As a result, a pull test of the multi-segment wire-bond may be higher than a single-segment wire-bond and the multi-segment wire-bond may resist cracking, lifting, or breaking.

Abstract: A semiconductor device includes a sense amplifier, a first magnetic tunneling junction (MTJ) connected to the sense amplifier at a first distance, a second MTJ connected to the sense amplifier at a second distance, and a third MTJ connected to the sense amplifier at a third distance. Preferably, the first distance is less than the second distance, the second distance is less than the third distance, a critical dimension of the first MTJ is less than a critical dimension of the second MTJ, and the critical dimension of the second MTJ is less than a critical dimension of the third MTJ.

Abstract: An organic light emitting display device including a light extraction reduction preventing layer disposed between a display unit disposed on a substrate and an encapsulation layer for protecting the display unit, which improves light emission efficiency by reducing an amount of light dissipating while light generated from an emission layer of the display unit is extracted to the outside.

Abstract: A semiconductor device has a first substrate and a first electrical component disposed over the first substrate. A first support frame is disposed over the first substrate. The first support frame has a horizontal support channel extending across the first substrate and a vertical support brace extending from the horizontal support channel to the first substrate. The first support frame can have a vertical shielding partition extending from the horizontal support channel to the first substrate. An encapsulant is deposited over the first electrical component and first substrate and around the first support frame. A second electrical component is disposed over the first electrical component. A second substrate is disposed over the first support frame. A second electrical component is disposed over the second substrate. A third substrate is disposed over the second substrate. A second support frame is disposed over the second substrate.

Abstract: A semiconductor device has a first package layer. A first shielding layer is formed over the first package layer. The first shielding layer is patterned to form a redistribution layer. An electrical component is disposed over the redistribution layer. An encapsulant is deposited over the electrical component. A second shielding layer is formed over the encapsulant. The second shielding layer is patterned. The patterning of the first shielding layer and second shielding layer can be done with a laser. The second shielding layer can be patterned to form an antenna.

Abstract: An integrated circuit and a method for designing an IC wherein the base or host chip is bonded to smaller chiplets via DBI technology. The bonding of chip to chiplet creates an uneven or multi-level surface of the overall chip requiring a releveling for future bonding. The uneven surface is built up with plating of bumps and subsequently releveled with various methods including planarization.

Abstract: Systems and methods are provided for a system in a package (SiP) connectivity using one or more ultra short reach (USR) chiplets. The USR chiplet can receive/transmit data at a lower throughput and transmit/receive that data at a higher throughput over ultra short distances. The USR chiplet can be connected to a main integrated circuit (IC) using a high density interconnect or integrated with the main IC in a mold material. The USR chip can enable the main IC to transfer data over a substrate at a higher speed using a fewer number of traces.

Abstract: In some examples a wafer chip scale package (WCSP) includes a semiconductor die having a device side in which a circuit is formed, and a redistribution layer (RDL) coupled to the device side that is positioned within an insulating member. In addition, the WCSP includes a scribe seal circumscribing the circuit along the device side, wherein the RDL abuts the scribe seal. Further, the WCSP includes a conductive member coupled to the RDL. The conductive member is configured to receive a solder member, and the insulating member does not extend along the device side of the semiconductor die between the conductive member and a portion of an outer perimeter of the WCSP closest to the conductive member.

Abstract: The present disclosure provides a package device. The package device includes a first integrated circuit chip, a second integrated circuit chip, a first input/output pin, and a first electrostatic discharge protection element. The first integrated circuit chip includes a first internal circuit and a first input/output pad disposed on the first integrated circuit chip and coupled to the first internal circuit. The second integrated circuit chip is stacked on the first integrated circuit chip. The second integrated circuit chip includes a second internal circuit and a second input/output pad disposed on the second integrated circuit chip and coupled to the second internal circuit. The first input/output pin is coupled to the first integrated circuit chip and the second integrated circuit chip. The first electrostatic discharge protection element is coupled between the first input/output pad and the first internal circuit.

Abstract: A chip package structure is provided. The chip package structure includes a chip. The chip package structure includes a conductive bump over and electrically connected to the chip. The chip package structure includes a ring-like structure over and electrically insulated from the chip. The ring-like structure surrounds the conductive bump, and the ring-like structure and the conductive bump are made of a same material.

Abstract: In an embodiment, a structure includes a core substrate, a redistribution structure coupled to a first side of the core substrate, the redistribution structure including a plurality of redistribution layers, each of the plurality of redistribution layers comprising a dielectric layer and a metallization layer, and a first local interconnect component embedded in a first redistribution layer of the plurality of redistribution layers, the first local interconnect component including a substrate, an interconnect structure on the substrate, and bond pads on the interconnect structure, the bond pads of the first local interconnect component physically contacting a metallization layer of a second redistribution layer, the second redistribution layer being adjacent the first redistribution layer, the metallization layer of the second redistribution layer comprising first conductive vias, the dielectric layer of the first redistribution layer encapsulating the first local interconnect component.

Abstract: Provided is a control module including a printed circuit board, an IC, and a shielding cover. The shielding cover is provided with a dispensing hole for adhesive dispensing. The IC is soldered onto the printed circuit board, and an adhesive may be dispensed between the IC and the printed circuit board through the dispensing hole. A method for manufacturing a control module is also provided.

Abstract: System, method, and silicon chip package for providing structural strength, heat dissipation and electrical connectivity using “W” shaped frame bonded to the one or more dies, wherein the “W” shaped frame provides compression strength to the silicon chip package when the one or more dies are bonded, and electrically conductivity between for the one or more dies to leads of silicon chip package, and heat dissipation for the silicon chip package.