Abstract: A device may include a multispectral filter array disposed on the substrate. The multispectral filter array may include a first metal mirror disposed on the substrate. The multispectral filter may include a spacer disposed on the first metal mirror. The spacer may include a set of layers. The spacer may include a second metal mirror disposed on the spacer. The second metal mirror may be aligned with two or more sensor elements of a set of sensor elements.

Abstract: The present disclosure provides a trench field effect transistor structure and a manufacturing method thereof. The manufacturing method includes: providing a substrate (100), forming an epitaxial layer (101), forming a device trench (102) in the epitaxial layer, and forming a shielding dielectric layer (107), a shielding gate layer (105), a first isolation dielectric layer (108), a gate dielectric layer (109), a gate layer (110), a second isolation dielectric layer (112), a body region (114), a source (115), a source contact hole (118), a source electrode structure (122), and a drain electrode structure (123). During manufacturing of a trench field effect transistor structure, a self-alignment process is adopted in a manufacturing process, so that a cell pitch is not limited by an exposure capability and alignment accuracy of a lithography machine, to further reduce the cell pitch of the device, improve a cell density, and reduce a device channel resistance.

Abstract: A display device includes a substrate, a circuit element layer on the substrate, a display element layer on the circuit element layer, a sealing film on the display element layer, an oxide film on the sealing film, a barrier metal layer on the oxide film, and a wiring layer on the barrier metal layer, wherein a surface of the sealing film in contact with the oxide film has concave/convexities, and the barrier metal layer is formed by titanium nitride. A height of the concave/convexities of the surface of the sealing film may be less than 30 nm. A thickness of the oxide film may be 5 nm or less.

Abstract: A method of manufacturing an organic light-emitting diode display comprising a substrate having a well-defined by a confinement structure, the well containing a first electrode and a second electrode spaced from each other, wherein the method may comprise depositing a light-emissive material in the well via ink-jet printing, thereby forming a substantially continuous light-emissive material layer in the well from the deposited light-emissive material, the light-emissive material layer spanning and contained within boundaries of the well, wherein a surface of the light-emissive material layer that faces away from the substrate has a non-planar topography. The method may further comprise positioning a common electrode over the light-emissive material layer.

Abstract: A semiconductor device includes a lower channel pattern and an upper channel pattern stacked on a substrate in a first direction perpendicular to a top surface of the substrate, lower source/drain patterns on the substrate and at a first side and a second side of the lower channel pattern, upper source/drain patterns stacked on the lower source/drain patterns and at a third side and a fourth side of the upper channel pattern, a first barrier pattern between the lower source/drain patterns and the upper source/drain patterns, and a second barrier pattern between the first barrier pattern and the upper source/drain patterns. The first barrier pattern includes a first material and the second barrier pattern includes a second material, wherein the first material and the second material are different.

Abstract: A flip chip package unit and associated packaging method. The flip chip package unit may include an integrated circuit (“IC”) die having a plurality of metal pillars formed on its first surface and attached to a rewiring substrate with the first surface of the IC die facing to the rewiring substrate, an under-fill material filling gaps between the first surface of the IC die and the rewiring substrate, and a thermal conductive protection film covering or overlaying and directly contacting with the entire second die surface and a first portion of sidewalls of the IC die. The thermal conductive protection film may have good thermal conductivity, uneasy to fall off from the IC die and can provide physical protection, electromagnetic interference protection and effective heat dissipation path to the IC die.

Abstract: An integrated circuit (IC) package comprising a-substrate having a first side and an opposing a second side, and a bridge die within the substrate. The bridge die comprises a plurality of vias extending from a first side to a second side of the bridge die. The bridge die comprises a first plurality of pads on the first side of the bridge die and a second plurality of pads on the second side. The plurality of vias interconnect ones of the first plurality of pads to ones of the second plurality of pads. The bridge die comprises an adhesive film over a layer of silicon oxide on the second side of the bridge die.

Abstract: Some embodiments include a memory device having a vertical stack of alternating insulative levels and conductive levels. Memory cells are along the conductive levels. The conductive levels have control gate regions which include a first vertical thickness, have routing regions which include a second vertical thickness that is less than the first vertical thickness, and have tapered transition regions between the first vertical thickness and the second vertical thickness. Charge-blocking material is adjacent to the control gate regions. Charge-storage material is adjacent to the charge-blocking material. Dielectric material is adjacent to the charge-storage material. Channel material extends vertically along the vertical stack and is adjacent to the dielectric material. The memory cells include the control gate regions, and include regions of the charge-blocking material, the charge-storage material, the dielectric material and the channel material.

Abstract: A semiconductor device package includes a first circuit layer, a first emitting device and a second emitting device. The first circuit layer has a first surface and a second surface opposite to the first surface. The first emitting device is disposed on the second surface of the first circuit layer. The first emitting device has a first surface facing the first circuit layer and a second surface opposite to the first surface. The first emitting device has a first conductive pattern disposed on the first surface of the first emitting device. The second emitting device is disposed on the second surface of the first emitting device. The second emitting device has a first surface facing the second surface of the first emitting device and a second surface opposite to the first surface. The second emitting device has a second conductive pattern disposed on the second surface of the emitting device.

Abstract: A semiconductor device includes a sense amplifier, a first magnetic tunneling junction (MTJ) connected to the sense amplifier at a first distance, a second MTJ connected to the sense amplifier at a second distance, and a third MTJ connected to the sense amplifier at a third distance. Preferably, the first distance is less than the second distance, the second distance is less than the third distance, a critical dimension of the first MTJ is less than a critical dimension of the second MTJ, and the critical dimension of the second MTJ is less than a critical dimension of the third MTJ.

Abstract: In a general aspect, a wire bonding apparatus can include a supply of bond wire, a wire bonding head, and an electrical continuity tester. The wire bonding head can including a wire cutter. The wire cutter can be electrically conductive. The electrical continuity tester can be coupled between the supply of bond wire and the wire cutter.

Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) chip comprising a semiconductor device that is inverted and that overlies a dielectric region inset into a top of a semiconductor substrate. An interconnect structure overlies the semiconductor substrate and the dielectric region and further comprises an intermetal dielectric (IMD) layer. The IMD layer is bonded to the top of the semiconductor substrate and accommodates a pad. A semiconductor layer overlies the interconnect structure, and the semiconductor device is in the semiconductor layer, between the semiconductor layer and the interconnect structure. The semiconductor device comprises a first source/drain electrode overlying the dielectric region and further overlying and electrically coupled to the pad. The dielectric region reduces substrate capacitance to decrease substrate power loss and may, for example, be a cavity or a dielectric layer. A contact extends through the semiconductor layer to the pad.

Abstract: A method for forming a three-dimensional (3D) memory device includes the following operations. First, in a first semiconductor structure, logic process-compatible devices and first bonding contacts are formed conductively connected to the logic process-compatible devices. In a second semiconductor structure, an array of NAND memory cells and second bonding contacts are formed conductively connected to the array of NAND memory cells. A first surface of an interposer structure is bonded to the second semiconductor structure. First interposer contacts disposed at the first surface of the interposer structure are conductively connected to the second bonding contacts. A second surface of the interposer structure is bonded to the first semiconductor structure. Second interposer contacts disposed at the second surface of the interposer structure are conductively connected to the first bonding contacts. The interposer structure is attached to the first semiconductor structure and the second semiconductor structure.

Abstract: The present disclosure provides a method of manufacturing a semiconductor device. The method includes providing an interconnection structure. The method also includes forming a first dielectric layer on the interconnection structure. The method further includes forming a sacrificial pattern on the first dielectric layer. The method also includes forming an RDL on the first dielectric layer and the sacrificial pattern. The method further includes removing the sacrificial pattern to form an air cavity within the RDL.

Abstract: The disclosure provides an electronic device, which includes a substrate, two adjacent transistors, a first scan line, and two adjacent light shielding elements. The two adjacent transistors are disposed on the substrate and arranged along a first direction. A first transistor of the two adjacent transistors includes a first active element and a first conductive element electrically connected to the first active element. The first scan line is extending along the first direction. The two adjacent light shielding elements are respectively disposed between the two adjacent transistors and the substrate. The two adjacent light shielding elements are spaced apart by a first gap region, and the first gap region overlaps the first conductive element. The display device of the disclosure can reduce the problem of image quality degradation caused by photo-leakage current.

Abstract: A display device includes a substrate. A first electrode is disposed on the substrate. A pixel definition layer is disposed on the substrate. A second electrode is disposed on the first electrode and the pixel definition layer. An organic emission layer is disposed between the first electrode and the second electrode. A planarization layer is disposed on the second electrode. A low refractive index layer is disposed on the planarization layer and overlaps the pixel definition layer. A high refractive index layer is disposed on the planarization layer and overlaps the second electrode. The high refractive index layer has a higher refractive index than that of the low refractive index layer.

Abstract: A saddle-gate source follower transistor is described, such as for integration with in-pixel circuitry of complementary metal-oxide semiconductor (CMOS) image sensor (CIS) pixels. The saddle-gate source-follower transistor structure can include a channel region having a three-dimensional geometry defined on its axial sides by trenches. A gate oxide layer is formed over the top and axial sides of the channel region, and a saddle-gate structure is formed on the gate oxide layer. As such, the saddle-gate structure includes a seat portion extending over the top of the channel region, and first and second fender portions extending over the first and second axial sides of the channel region, such that the first and second fender portions are buried below an upper surface of the semiconductor substrate (e.g., buried into trenches formed in side isolation regions).

Abstract: Methods for forming channel structures in 3D memory devices are disclosed. In one example, a memory film and a sacrificial layer are subsequently formed along a sidewall and a bottom of a channel hole. A protective structure covering a portion of the sacrificial layer along the sidewall of the channel hole is formed. A portion of the sacrificial layer at the bottom of the channel hole that is not covered by the protective structure is wet etched. A portion of the memory film at the bottom of the channel hole that is not covered by a remainder of the sacrificial layer is wet etched.

Abstract: A three-dimensional semiconductor device is provided. The three-dimensional device may include substrate; a common electrode layer on the substrate; a word line stack disposed on the common electrode layer, the word line stack having interlayer insulating layers and word lines structures alternately stacked and; and a vertical channel pillar penetrating the word line stack, the vertical channel pillar being electrically connected to the common electrode layer. Each of the word line structures includes a body portion having a first vertical width and an extension portion having a second vertical width greater than the first vertical width. The extension portion abuts the vertical channel pillar.

Abstract: A package that includes a substrate, an integrated device coupled to the substrate, an encapsulation layer located over the substrate, at least one encapsulation layer interconnect located in the encapsulation layer, and a metal layer located over the encapsulation layer. The substrate includes at least one dielectric layer and a plurality of interconnects. The encapsulation layer interconnect is coupled to the substrate. The metal layer is configured as an electromagnetic interference (EMI) shield for the package. The metal layer is located over a backside of the integrated device.