Abstract: A 3D flash memory device such as a 3D AND flash memory device is provided. The 3D flash memory device includes a substrate, a conductive layer, a 3D flash memory array, and through-array vias (TAVs). The substrate includes a memory cell region and a passive device region. The conductive layer is formed on the substrate, and the conductive layer includes: a first circuit disposed at the memory cell region and a second circuit of a passive device disposed at the passive device region. The 3D flash memory array is formed on the first circuit of the memory cell region. The TAVs are respectively formed on the second circuit of the passive device disposed at the passive device region and connected to at least one end of the second circuit.
Abstract: An image sensor includes a semiconductor substrate, a gate dielectric layer, a gate electrode, a protection oxide film, and a nitride hard mask. The gate dielectric layer is over the semiconductor substrate. The gate electrode is over the gate dielectric layer. An entirety of a first portion of the gate dielectric layer directly under the gate electrode is of uniform thickness. The protection oxide film is in contact with a top surface of the gate electrode. The gate dielectric layer extends beyond a sidewall of the protection oxide film. The nitride hard mask is in contact with a top surface of the protection oxide film.
Abstract: Provided herein are approaches for forming an image sensor with increased well depth due to cryogenic ion channeling of ultra-high energy (UHE) ions. In some embodiments, a method may include providing a wafer of a semiconductor device, the semiconductor device including a photoelectric conversion region, and cooling the wafer to a temperature less than ?50° C. The method may further include performing an ion implant to the photoelectric conversion region to form a photodiode well after cooling the wafer.
Type:
Grant
Filed:
October 7, 2020
Date of Patent:
November 28, 2023
Assignee:
Applied Materials, Inc.
Inventors:
Hans-Joachim L. Gossmann, Stanislav S. Todorov, Hiroyuki Ito
Abstract: Embodiments of the present disclosure generally relate to methods of cleaning a structure and methods of depositing a capping layer in a structure. The method of cleaning a structure includes suppling a cleaning gas, including a first gas including nitrogen (N) and a second gas including fluorine (F), to a bottom surface of a structure. The cleaning gas removes unwanted metal oxide and etch residue from the bottom surface of the structure. The method of depositing a capping layer includes depositing the capping layer over the bottom surface of the structure. The methods described herein reduce the amount of unwanted metal oxides and residue, which improves adhesion of deposited capping layers.
Type:
Grant
Filed:
January 20, 2021
Date of Patent:
November 28, 2023
Assignee:
Applied Materials, Inc.
Inventors:
Naomi Yoshida, He Ren, Hao Jiang, Chenfei Shen, Chi-Chou Lin, Hao Chen, Xuesong Lu, Mehul B. Naik
Abstract: An image sensor with high quantum efficiency is provided. In some embodiments, a semiconductor substrate includes a non-porous semiconductor layer along a front side of the semiconductor substrate. A periodic structure is along a back side of the semiconductor substrate. A high absorption layer lines the periodic structure on the back side of the semiconductor substrate. The high absorption layer is a semiconductor material with an energy bandgap less than that of the non-porous semiconductor layer. A photodetector is in the semiconductor substrate and the high absorption layer. A method for manufacturing the image sensor is also provided.
Abstract: An embodiment is a device including a first fin extending from a substrate, a first gate stack over and along sidewalls of the first fin, a first gate spacer disposed along a sidewall of the first gate stack, and a first source/drain region in the first fin and adjacent the first gate spacer. The first source/drain region including a first insulator layer on the first fin, and a first epitaxial layer on the first insulator layer.
Abstract: An electronics package includes an electrically insulating substrate having a first surface and a second surface, an adhesive layer positioned on the first surface of the electrically insulating substrate, and an electrical component having a top surface coupled to the adhesive layer on a surface thereof opposite the electrically insulating substrate, the electrical component having contact pads on the top surface. Vias are formed through the electrically insulating substrate and the adhesive layer at locations corresponding to the contact pads by way of a mechanical punching operation, with each of the vias having a via wall extending from the second surface of the electrically insulating substrate to a respective contact pad. At each via, the electrically insulating substrate comprises a protrusion extending outwardly from the first surface thereof so as to cover at least part of the adhesive layer in forming part of the via wall.
Type:
Grant
Filed:
June 9, 2022
Date of Patent:
November 21, 2023
Assignee:
General Electric Company
Inventors:
Christopher James Kapusta, Youichi Nishihara
Abstract: Semiconductor devices including electrically-isolated extensions and associated systems and methods are disclosed herein. An electrically-isolated extension may be coupled to a corresponding connection pad that is attached to a surface of a device. The electrically-isolated extensions may extend at least partially through one or more layers at or near the surface and toward a substrate or an inner portion thereof.
Abstract: A semiconductor package structure includes a conductive pad formed over a substrate. The structure also includes a passivation layer formed over the conductive pad. The structure also includes a first via structure formed through the passivation layer and in contact with the conductive pad. The structure also includes a first encapsulating material surrounding the first via structure. The structure also includes a redistribution layer structure formed over the first via structure. The first via structure has a lateral extending portion embedded in the first encapsulating material near a top surface of the first via structure.
Abstract: A bonded structure can include a first reconstituted element comprising a first element and having a first side comprising a first bonding surface and a second side opposite the first side. The first reconstituted element can comprise a first protective material disposed about a first sidewall surface of the first element. The bonded structure can comprise a second reconstituted element comprising a second element and having a first side comprising a second bonding surface and a second side opposite the first side. The first reconstituted element can comprise a second protective material disposed about a second sidewall surface of the second element. The second bonding surface of the first side of the second reconstituted element can be directly bonded to the first bonding surface of the first side of the first reconstituted element without an intervening adhesive along a bonding interface.
Type:
Grant
Filed:
December 28, 2021
Date of Patent:
November 14, 2023
Assignee:
ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
Inventors:
Belgacem Haba, Rajesh Katkar, Ilyas Mohammed, Javier A. DeLaCruz
Abstract: In certain embodiments, a semiconductor device includes a substrate having an n-doped well feature and an epitaxial silicon germanium fin formed over the n-doped well feature. The epitaxial silicon germanium fin has a lower part and an upper part. The lower part has a lower germanium content than the upper part. A channel is formed from the epitaxial silicon germanium fin. A gate is formed over the epitaxial silicon germanium fin. A doped source-drain is formed proximate the channel.
Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A channel opening extending vertically is formed above a substrate. A semiconductor plug is formed in a lower portion of the channel opening. A memory film and a channel sacrificial layer are subsequently formed above the semiconductor plug and along a sidewall of the channel opening. A semiconductor plug protrusion protruding above the semiconductor plug and through a bottom of the memory film and the channel sacrificial layer is formed. A cap layer is formed in the channel opening and over the channel sacrificial layer. The cap layer covers the semiconductor plug protrusion. A semiconductor channel is formed between the memory film and the cap layer by replacing the channel sacrificial layer with a semiconductor material epitaxially grown from the semiconductor plug protrusion.
Abstract: A semiconductor device includes first and second members. In the first member, a first electronic circuit including a semiconductor element is formed. The second member is joined to an area of part of a first surface of the first member, and includes a second electronic circuit including a semiconductor element formed of a semiconductor material different from that of the semiconductor element of the first electronic circuit. An interlayer insulating film covers the second member and an area of the first surface of the first member to which the second member is not joined. An inter-member connection wire on the interlayer insulating film couples the first and second electronic circuits through an opening in the interlayer insulating film. A shield structure including a first metal pattern disposed on the interlayer insulating film shields a shielded circuit, which is part of the first electronic circuit, in terms of radio frequencies.
Abstract: A method for evaluation of thin film non-uniform stress using high order wafer warpage, the steps including measuring a net wafer warpage across a wafer area due to thin film deposition, fitting a two dimensional low-order polynomial to the wafer warpage measurements and subtracting the low-order polynomial from the net wafer warpage across the wafer area.
Abstract: A light emitting stacked structure including a first epitaxial stack including a first n-type semiconductor layer, a first p-type semiconductor layer, and a first active layer disposed therebetween, a second epitaxial stack disposed on the first epitaxial stack and including a second n-type semiconductor layer, a second p-type semiconductor layer, and a second active layer disposed therebetween, a third epitaxial stack disposed on the second epitaxial layer and including a third n-type semiconductor layer, a third p-type semiconductor layer, and a third active layer disposed therebetween, and a shared electrode disposed between two adjacent epitaxial stacks facing each other, in which two semiconductor layers of the two adjacent epitaxial stacks with the shared electrode therebetween have a same polarity.
Type:
Grant
Filed:
January 4, 2021
Date of Patent:
October 31, 2023
Assignee:
Seoul Viosys Co., Ltd.
Inventors:
Jong Hyeon Chae, Seong Gyu Jang, Ho Joon Lee
Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack including interleaved conductive layers and dielectric layers above the substrate, and a channel structure extending vertically through the memory stack. The channel structure includes a high dielectric constant (high-k) dielectric layer disposed continuously along a sidewall of the channel structure, a memory film over the high-k dielectric layer along the sidewall of the channel structure, and a semiconductor channel over the memory film along the sidewall of the channel structure.
Type:
Grant
Filed:
May 22, 2020
Date of Patent:
October 24, 2023
Assignee:
YANGTZE MEMORY TECHNOLOGIES CO., LTD.
Inventors:
Shuangshuang Peng, Jingjing Geng, Jiajia Wu, Tuo Li
Abstract: A semiconductor package structure and a method of manufacturing the same are provided. The semiconductor package structure includes a first electronic component, a second electronic component, and a reinforcement component. The reinforcement component is disposed above the first electronic component and the second electronic component. The reinforcement component is configured to reduce warpage.
Type:
Grant
Filed:
July 15, 2021
Date of Patent:
October 24, 2023
Assignee:
ADVANCED SEMICONDUCTOR ENGINEERING, INC.
Abstract: A quantum device (100) includes an interposer (112), a quantum chip (111) mounted on the interposer (112), and a shield part (150) provided so as to surround a quantum circuit region of the interposer (112) and the quantum chip (111). Accordingly, the quantum device (100) is able to prevent interference in the quantum circuit region due to exogenous noise.
Abstract: A semiconductor device includes a semiconductor chip including an electrical contact arranged on a main surface of the semiconductor chip, an external connection element configured to provide a first electrical connection between the semiconductor device and a printed circuit board, and an electrical redistribution layer extending in a direction parallel to the main surface of the semiconductor chip and configured to provide a second electrical connection between the electrical contact of the semiconductor chip and the external connection element. The electrical redistribution layer includes a ground line connected to a ground potential and a signal line configured to carry an electrical signal having a wavelength.
Type:
Grant
Filed:
November 29, 2021
Date of Patent:
October 24, 2023
Assignee:
Infineon Technologies AG
Inventors:
Walter Hartner, Francesca Arcioni, Tuncay Erdoel, Vincenzo Fiore, Helmut Kollmann, Arif Roni, Emanuele Stavagna, Christoph Wagner
Abstract: Provided is a display device including a substrate including a display area including a plurality of pixel areas, and a non-display area outside the display area, a pixel circuit layer including a plurality of circuit elements in the display area, a display element layer including a plurality of light-emitting elements in the display area on the pixel circuit layer, and first and second alignment lines on the substrate, and each including a main line at the same layer as at least one electrode on the display element layer, and a sub line electrically connected to the main line and at the same layer as at least one electrode on the pixel circuit layer, wherein the first alignment line and the second alignment line do not include the main line in the non-display area, and include the sub line to be spaced apart from one edge of the substrate.
Type:
Grant
Filed:
August 11, 2022
Date of Patent:
October 24, 2023
Assignee:
Samsung Display Co., Ltd.
Inventors:
Sung Jin Lee, Jin Yeong Kim, Jin Taek Kim, Soo Hyun Moon, Tae Hoon Yang, Seung Min Lee