Patents Examined by Didarul Mazumder
  • Patent number: 10418578
    Abstract: This disclosure provides a quantum dot light-emitting diode comprising a first electron layer, an organic light-emitting layer, a first hole layer, a second electron layer, a quantum dot light-emitting layer, and a second hole layer. The first electron layer and the first hole layer are configured to transport first electrons and first holes to the organic light-emitting layer. The organic light-emitting layer is configured to emit a first light by recombining the first electrons and the first holes. The second electron layer and the second hole layer are configured to transport second electrons and second holes to the quantum dot light-emitting layer. The quantum dot light-emitting layer is configured to emit a second light by recombining the second electrons and the second holes.
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: September 17, 2019
    Assignee: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
    Inventors: Wei Yuan, Shibo Jiao
  • Patent number: 10418522
    Abstract: An optoelectronic device and method of manufacturing an optoelectronic device are disclosed. The optoelectronic device includes a substrate; a semiconductor comprising an n-type layer disposed on the substrate, a p-type layer disposed on the n-type layer, and an active layer disposed between the n-type layer and the p-type layer; a transition layer disposed on the substrate and located between the n-type layer and the substrate, the transition layer including an oxygenated IIIA-transition metal nitride; and a p-contact layer disposed on the p-type layer of the semiconductor.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: September 17, 2019
    Assignee: GOFORWARD TECHNOLOGY INC.
    Inventors: Yangang Xi, Jiguang Li
  • Patent number: 10410996
    Abstract: An integrated circuit IC package with one or more pins protruding from the IC package for electrically connecting the IC package with a printed circuit board PCB is presented. The IC package has a first die with a first electronic component, a second die with a second electronic component, and a conductive plate having a plane surface. The first electronic component may be a semiconductor power device and the second electronic component may be a control circuit. The plane surface of the conductive plate is electrically connected to both a plane surface of the first die and one or more pins such that an electrical connection is established between the first die and the one or more pins. The second die may be arranged on top of the conductive plate. Alternatively, a third die with a third electronic component may be arranged on top of the conductive plate.
    Type: Grant
    Filed: December 2, 2016
    Date of Patent: September 10, 2019
    Assignee: Dialog Semiconductor (UK) Limited
    Inventors: Melvin Martin, Baltazar Canete, Jr., Macario Campos, Rajesh Aiyandra
  • Patent number: 10403750
    Abstract: A Lateral Diffusion Metal Oxide Semiconductor (LDMOS) device and its manufacturing method are presented. The LDMOS device comprises a first region that has a first conductivity type; a drift region that has a second conductivity type in the first region, wherein the second conductivity type is opposite to the first conductivity type; and a plurality of second regions that have the first conductivity type in the drift region, wherein the second regions are separated from each other and extend to the first region along a depth direction of the drift region. This LDMOS device has an higher Breakdown Voltage and thus better performance than conventional LDMOS devices.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: September 3, 2019
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventor: Lei Fang
  • Patent number: 10403745
    Abstract: A nitride semiconductor device includes a horizontal switching device that includes a substrate, a channel forming layer, a source region, a drain region and a gate region. The source region and the drain region are arranged apart from each other in one direction along a plane of the substrate. The gate region is formed of a p-type semiconductor layer and is arranged between the source region and the drain region. The gate region is divided into multiple parts in a perpendicular direction along the plane of the substrate, the perpendicular direction being perpendicular to an arrangement direction in which the source region and the drain region are arranged. Accordingly, on-resistance is decreased while securing high breakdown voltage.
    Type: Grant
    Filed: June 14, 2016
    Date of Patent: September 3, 2019
    Assignee: DENSO CORPORATION
    Inventors: Yasushi Higuchi, Shinichi Hoshi, Kazuhiro Oyama
  • Patent number: 10403752
    Abstract: An embodiment includes an apparatus comprising: a fin structure on a substrate, the fin structure including fin top and bottom portions, a channel including a majority carrier, and an epitaxial (EPI) layer; an insulation layer including insulation layer top and bottom portions adjacent the fin top and bottom portions; wherein (a) the EPI layer comprises one or more of group IV and lll-V materials, (b) the fin bottom portion includes a fin bottom portion concentration of dopants of opposite polarity to the majority carrier, (c) the fin top portion includes a fin top portion concentration of the dopants less than the fin bottom portion concentration, (d) the insulation layer bottom portion includes an insulation layer bottom portion concentration of the dopants, and (e) the insulation layer top portion includes an insulation top layer portion concentration greater than the insulation bottom portion concentration. Other embodiments are described herein.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: September 3, 2019
    Assignee: Intel Corporation
    Inventors: Karthik Jambunathan, Glenn A. Glass, Chandra S. Mohapatra, Anand S. Murthy, Stephen M. Cea, Tahir Ghani
  • Patent number: 10396181
    Abstract: A semiconductor device comprises a nanowire arranged over a substrate, a gate stack arranged around the nanowire, a spacer arranged along a sidewall of the gate stack, a cavity defined by a distal end of the nanowire and the spacer, and a source/drain region partially disposed in the cavity and in contact with the distal end of the nanowire.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: August 27, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Marc A. Bergendahl, Kangguo Cheng, Fee Li Lie, Eric R. Miller, Jeffrey C. Shearer, John R. Sporre, Sean Teehan
  • Patent number: 10396111
    Abstract: A package for an optical sensor, comprises an optically opaque enclosure for forming a cavity when mounted onto a substrate and an optical element based on an optically translucent polymer. An aperture in the enclosure is designed to attach the optical element to the enclosure.
    Type: Grant
    Filed: June 25, 2014
    Date of Patent: August 27, 2019
    Assignee: ams AG
    Inventors: Arnold Umali, Harald Etschmaier, Guenter Aflenzer
  • Patent number: 10388699
    Abstract: A three-dimensional semiconductor memory device includes first to third cell array layers sequentially stacked on a substrate. Each of the first to third cell array layers includes memory cells arranged along first and second directions crossing each other and parallel to a top surface of the substrate. Each of the memory cells includes a variable resistance element and a tunnel field effect transistor connected in series. The device further includes bit lines extending along the first direction between the first and second cell array layers and at least one source line extending along either the first direction or the second direction between the second and third cell array layers. The memory cells of the first and second cell array layers share the bit lines, and the memory cells of the second and third cell array layers share the source line.
    Type: Grant
    Filed: May 4, 2017
    Date of Patent: August 20, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Mu-Hui Park, Wooyeong Cho
  • Patent number: 10381330
    Abstract: A method of bonding a first substrate to a second substrate, wherein the first substrate includes first electrical contacts on a top surface of the first substrate, and wherein the second substrate includes second electrical contacts on a bottom surface of the second substrate. The method includes forming a block of polyimide on the top surface of the first substrate, wherein the block of polyimide has a rounded upper corner, and vertically moving the top surface of the first substrate and the bottom surface of the second substrate toward each other until the first electrical contacts abut the second electrical contacts, wherein during the moving, the second substrate makes contact with the rounded upper corner of the polyimide causing the first and second substrates to move laterally relative to each other.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: August 13, 2019
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Justin Hiroki Sato, Bomy Chen, Walter Lundy
  • Patent number: 10374012
    Abstract: Provided herein may be an electronic device including a semiconductor memory. The semiconductor memory may include: first column lines and sub-column lines extending in a first direction; first row lines extending in a second direction; first tiles including first memory cells connected between the first column lines and the first row lines; first contact plugs coupled to the sub-column lines and disposed between the first tiles in the first direction; second contact plugs coupled to the first row lines and disposed between the first tiles in the second direction; and a first connection structure partially coupling the first column lines to the sub-column lines such that the longer a current path on a first row line from a selected first memory cell to the corresponding second contact plug, the shorter a current path from the selected first memory cell to the corresponding first contact plug.
    Type: Grant
    Filed: July 9, 2018
    Date of Patent: August 6, 2019
    Assignee: SK HYNIX INC.
    Inventor: Dong Hoon Kim
  • Patent number: 10374193
    Abstract: A cracks propagation preventing, polarization film attaches to outer edges of a lower inorganic layer of an organic light emitting diodes display where the display is formed on a flexible substrate having the lower inorganic layer blanket formed thereon. The organic light emitting diodes display further includes a display unit positioned on the inorganic layer and including a plurality of organic light emitting diodes configured to display an image, and a thin film encapsulating layer covering the display unit and joining with edges of the inorganic layer extending beyond the display unit.
    Type: Grant
    Filed: September 19, 2017
    Date of Patent: August 6, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Chung Yi, Sang-Hun Oh
  • Patent number: 10373986
    Abstract: An array substrate, a display panel and a display device, including at least two gate lines in a display area, a gate driving circuit and at least two gate fan-out lines in a non-display are described. One end of each of the gate fan-out lines are electrically connected with one signal output of the gate driving circuit and the other end of each of the gate fan-out lines are electrically connected with the gate lines. By configuring a first gate fan-out line of the gate fan-out lines and the gate driving circuit to have an overlapping area outside a mutual connection area, an area where the gate fan-out lines are overlaps the gate driving circuit, space occupied by the first gate fan-out line outside the gate driving circuit is decreased to shorten a distance between the gate driving circuit and the display area.
    Type: Grant
    Filed: February 12, 2018
    Date of Patent: August 6, 2019
    Assignee: XIAMEN TIANMA MICRO-ELECTRONICS CO., LTD.
    Inventors: Guochang Lai, Junyi Li, Zhongjie Zhang
  • Patent number: 10370240
    Abstract: A layer structure may include a carrier, a two-dimensional layer, and a holding structure. The holding structure is arranged on the carrier and holds the two-dimensional layer on the carrier such that at least a portion of the two-dimensional layer is spaced apart from the carrier. The holding structure includes a holding portion extending from the two-dimensional layer towards the carrier beyond the at least a portion of the two-dimensional layer spaced apart from the carrier.
    Type: Grant
    Filed: July 11, 2017
    Date of Patent: August 6, 2019
    Assignee: Infineon Technologies AG
    Inventors: Matthias Koenig, Guenther Ruhl
  • Patent number: 10366950
    Abstract: Embodiments of the invention include an interconnect structure with a via and methods of forming such structures. In an embodiment, the interconnect structure comprises a first interlayer dielectric (ILD). A first interconnect line and a second interconnect line extend into the first ILD. According to an embodiment, a second ILD is positioned over the first interconnect line and the second interconnect line. A via may extend through the second ILD and electrically coupled to the first interconnect line. Additionally, embodiments of the invention include a portion of a bottom surface of the via being positioned over the second interconnect line. However, an isolation layer may be positioned between the bottom surface of the via and a top surface of the second interconnect line, according to an embodiment of the invention.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: July 30, 2019
    Assignee: Intel Corporation
    Inventors: Kevin Lin, Robert Lindsey Bristol, James M. Blackwell, Rami Hourani
  • Patent number: 10361159
    Abstract: A semiconductor device includes a substrate having a plurality of fins protruding therefrom and an active region on the fins. The device further includes a contact including a conductive region having a concave portion defining an upper portion and a lower portion of the conductive region, an interlayer insulating layer on the active region, and a side insulating layer interposed between the interlayer insulating layer and the lower portion of the conductive region.
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: July 23, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jong Ho You, Sang Young Kim, Byung Chan Ryu
  • Patent number: 10355048
    Abstract: An isolation structure is disposed between fin field effect transistors of a magnetic random access memory (MRAM) device. The isolation structure includes a fin line substrate, having a trench crossing the fin line substrate. An oxide layer is disposed on the fin line substrate other than the trench. A liner layer is disposed on an indent surface of the trench. A nitride layer is disposed on the liner layer, partially filling the trench. An oxide residue is disposed on the nitride layer within the trench at a bottom portion of the trench. A gate-like structure is disposed on the oxide layer and also fully filling the trench.
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: July 16, 2019
    Assignee: United Microelectronics Corp.
    Inventors: Chung-Liang Chu, Yu-Ruei Chen, Hung-Yueh Chen, Yu-Ping Wang
  • Patent number: 10354876
    Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a substrate and a material layer. The substrate has a first region, and the material layer is disposed on the substrate. The material layer includes plural of first patterns and plural of second patterns arranged in an array, and two third patterns. The first patterns are disposed within the first region, the second patterns are disposed at two opposite outer sides of the first region, and the third patterns are disposed at another two opposite outer sides of the first region, wherein each of the third patterns partially merges each of a part of the first patterns and each of a part of the second patterns.
    Type: Grant
    Filed: June 24, 2018
    Date of Patent: July 16, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Yu-Cheng Tung, Fu-Che Lee, Ying-Chih Lin
  • Patent number: 10354978
    Abstract: A stacked package has plurality of chip packages stacked on active surfaces of each other, a dielectric layer, a redistribution layer and a plurality of external terminals. Each chip package has an exterior conductive element formed on the active surface. Each exterior conductive element has a cut edge exposed on at least one of the lateral side of the chip package. The dielectric layer, the redistribution layer and the external terminals are formed in sequence on the lateral side with the exposed cut edges to form the electrical connection between the cut edges, the redistribution layer and the external terminals. Therefore, the process for forming the electrical connections is simplified to enhance the reliability and the UPH for manufacturing the stacked package.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: July 16, 2019
    Assignee: POWERTECH TECHNOLOGY INC.
    Inventors: Ming-Chih Chen, Hung-Hsin Hsu, Yuan-Fu Lan, Chi-An Wang, Hsien-Wen Hsu
  • Patent number: 10343895
    Abstract: A method for forming a micro-electro-mechanical system (MEMS) device structure is provided. The MEMS device structure includes a micro-electro-mechanical system (MEMS) substrate, and a substrate formed over the MEMS substrate. The substrate includes a semiconductor via through the substrate. The MEMS device structure includes a dielectric layer formed over the substrate and a polymer layer formed on the dielectric layer. The MEMS device structure also includes a conductive layer formed in the dielectric layer and the polymer layer. The conductive layer is electrically connected to the semiconductor via, and the polymer layer is between the conductive layer and the dielectric layer.
    Type: Grant
    Filed: February 14, 2018
    Date of Patent: July 9, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kai-Fung Chang, Lien-Yao Tsai, Len-Yi Leu